<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
<meta name="generator" content="Doxygen 1.8.5"/>
<title>v_hdmirx1: xv_hdmirx1_hw.h File Reference</title>
<link href="tabs.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="jquery.js"></script>
<script type="text/javascript" src="dynsections.js"></script>
<link href="navtree.css" rel="stylesheet" type="text/css"/>
<script type="text/javascript" src="resize.js"></script>
<script type="text/javascript" src="navtree.js"></script>
<script type="text/javascript">
  $(document).ready(initResizable);
  $(window).load(resizeHeight);
</script>
<link href="doxygen.css" rel="stylesheet" type="text/css" />
<link href="HTML_custom.css" rel="stylesheet" type="text/css"/>
</head>
<body>
<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
<div id="titlearea">
<table cellspacing="0" cellpadding="0">
 <tbody>
 <tr style="height: 56px;">
  <td id="projectlogo"><img alt="Logo" src="xlogo_bg.png"/></td>
  <td style="padding-left: 0.5em;">
   <div id="projectname">v_hdmirx1
   </div>
   <div id="projectbrief">Vitis Drivers API Documentation</div>
  </td>
 </tr>
 </tbody>
</table>
</div>
<!-- end header part -->
<!-- Generated by Doxygen 1.8.5 -->
  <div id="navrow1" class="tabs">
    <ul class="tablist">
      <li><a href="index.html"><span>Overview</span></a></li>
      <li><a href="annotated.html"><span>Data&#160;Structures</span></a></li>
      <li><a href="globals.html"><span>APIs</span></a></li>
      <li><a href="files.html"><span>File&#160;List</span></a></li>
    </ul>
  </div>
</div><!-- top -->
<div id="side-nav" class="ui-resizable side-nav-resizable">
  <div id="nav-tree">
    <div id="nav-tree-contents">
      <div id="nav-sync" class="sync"></div>
    </div>
  </div>
  <div id="splitbar" style="-moz-user-select:none;" 
       class="ui-resizable-handle">
  </div>
</div>
<script type="text/javascript">
$(document).ready(function(){initNavTree('xv__hdmirx1__hw_8h.html','');});
</script>
<div id="doc-content">
<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">xv_hdmirx1_hw.h File Reference</div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This header file contains identifiers and register-level core functions (or macros) that can be used to access the Xilinx HDMI RX core. </p>
<p>For more information about the operation of this core see the hardware specification and documentation in the higher level driver <a class="el" href="xv__hdmirx1_8h.html" title="This is the main header file for Xilinx HDMI RX core. ">xv_hdmirx1.h</a> file.</p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who    Date     Changes
</p>
<hr/>
<p>
1.00  EB     02/05/19 Initial release.
</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ab0b72058c3659fc9bbb2c202270bd1a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab0b72058c3659fc9bbb2c202270bd1a2">XV_HDMIRX1_HW_H_</a></td></tr>
<tr class="memdesc:ab0b72058c3659fc9bbb2c202270bd1a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#ab0b72058c3659fc9bbb2c202270bd1a2">More...</a><br/></td></tr>
<tr class="separator:ab0b72058c3659fc9bbb2c202270bd1a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a98c2ec7a077e707ff67302d576ba468f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a98c2ec7a077e707ff67302d576ba468f">XV_HDMIRX1_VER_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(0*4))</td></tr>
<tr class="memdesc:a98c2ec7a077e707ff67302d576ba468f"><td class="mdescLeft">&#160;</td><td class="mdescRight">VER Identification Register offset.  <a href="#a98c2ec7a077e707ff67302d576ba468f">More...</a><br/></td></tr>
<tr class="separator:a98c2ec7a077e707ff67302d576ba468f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8b63858c4f1f73528819cac7258bc730"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a8b63858c4f1f73528819cac7258bc730">XV_HDMIRX1_VER_VERSION_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(1*4))</td></tr>
<tr class="memdesc:a8b63858c4f1f73528819cac7258bc730"><td class="mdescLeft">&#160;</td><td class="mdescRight">VER Version Register offset.  <a href="#a8b63858c4f1f73528819cac7258bc730">More...</a><br/></td></tr>
<tr class="separator:a8b63858c4f1f73528819cac7258bc730"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7c9d08be5e87e6fd62df99abfd8d3a07"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7c9d08be5e87e6fd62df99abfd8d3a07">XV_HDMIRX1_VCKE_SYS_CNT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(2*4))</td></tr>
<tr class="memdesc:a7c9d08be5e87e6fd62df99abfd8d3a07"><td class="mdescLeft">&#160;</td><td class="mdescRight">VCKE System Counts Register offset.  <a href="#a7c9d08be5e87e6fd62df99abfd8d3a07">More...</a><br/></td></tr>
<tr class="separator:a7c9d08be5e87e6fd62df99abfd8d3a07"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adfbfa70ecfc15e9951eed4a41333b8e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#adfbfa70ecfc15e9951eed4a41333b8e1">XV_HDMIRX1_SR_SSB_ERR_CNT0_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(3*4))</td></tr>
<tr class="memdesc:adfbfa70ecfc15e9951eed4a41333b8e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">SR/SSB period error 0 counter register offset.  <a href="#adfbfa70ecfc15e9951eed4a41333b8e1">More...</a><br/></td></tr>
<tr class="separator:adfbfa70ecfc15e9951eed4a41333b8e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae366ca39c9b39631eedf90c9df008502"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae366ca39c9b39631eedf90c9df008502">XV_HDMIRX1_SR_SSB_ERR_CNT1_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(4*4))</td></tr>
<tr class="memdesc:ae366ca39c9b39631eedf90c9df008502"><td class="mdescLeft">&#160;</td><td class="mdescRight">SR/SSB period error 1 counter register offset.  <a href="#ae366ca39c9b39631eedf90c9df008502">More...</a><br/></td></tr>
<tr class="separator:ae366ca39c9b39631eedf90c9df008502"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a38593421477cf0920a8c26ca2cc02844"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a38593421477cf0920a8c26ca2cc02844">XV_HDMIRX1_SR_SSB_ERR_CNT2_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(5*4))</td></tr>
<tr class="memdesc:a38593421477cf0920a8c26ca2cc02844"><td class="mdescLeft">&#160;</td><td class="mdescRight">SR/SSB period error 2 counter register offset.  <a href="#a38593421477cf0920a8c26ca2cc02844">More...</a><br/></td></tr>
<tr class="separator:a38593421477cf0920a8c26ca2cc02844"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a280f061931e044ccdc8aa667114f17e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a280f061931e044ccdc8aa667114f17e5">XV_HDMIRX1_SR_SSB_ERR_CNT3_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(6*4))</td></tr>
<tr class="memdesc:a280f061931e044ccdc8aa667114f17e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">SR/SSB period error 3 counter register offset.  <a href="#a280f061931e044ccdc8aa667114f17e5">More...</a><br/></td></tr>
<tr class="separator:a280f061931e044ccdc8aa667114f17e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa7d3866d8c4fe0eb40668892c8907a6e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa7d3866d8c4fe0eb40668892c8907a6e">XV_HDMIRX1_DBG_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(7*4))</td></tr>
<tr class="memdesc:aa7d3866d8c4fe0eb40668892c8907a6e"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL word aligner tap select changed register offset.  <a href="#aa7d3866d8c4fe0eb40668892c8907a6e">More...</a><br/></td></tr>
<tr class="separator:aa7d3866d8c4fe0eb40668892c8907a6e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a65be302ae67526fd5247ed8bb7d992eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a65be302ae67526fd5247ed8bb7d992eb">XV_HDMIRX1_SR_SSB_ERR1_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a65be302ae67526fd5247ed8bb7d992eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL SR/SSB period error during training period shift.  <a href="#a65be302ae67526fd5247ed8bb7d992eb">More...</a><br/></td></tr>
<tr class="separator:a65be302ae67526fd5247ed8bb7d992eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a601ed84adad6a742a16572b1394049f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a601ed84adad6a742a16572b1394049f7">XV_HDMIRX1_SR_SSB_ERR1_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a601ed84adad6a742a16572b1394049f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL SR/SSB period error during training period mask.  <a href="#a601ed84adad6a742a16572b1394049f7">More...</a><br/></td></tr>
<tr class="separator:a601ed84adad6a742a16572b1394049f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a505ad0065028146badda00bb46ef8100"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a505ad0065028146badda00bb46ef8100">XV_HDMIRX1_SR_SSB_ERR2_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a505ad0065028146badda00bb46ef8100"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL SR/SSB period error during NON-training period shift.  <a href="#a505ad0065028146badda00bb46ef8100">More...</a><br/></td></tr>
<tr class="separator:a505ad0065028146badda00bb46ef8100"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ace563a6b75eaca93062466c5fb31d3c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ace563a6b75eaca93062466c5fb31d3c8">XV_HDMIRX1_SR_SSB_ERR2_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:ace563a6b75eaca93062466c5fb31d3c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL SR/SSB period error during NON-training period mask.  <a href="#ace563a6b75eaca93062466c5fb31d3c8">More...</a><br/></td></tr>
<tr class="separator:ace563a6b75eaca93062466c5fb31d3c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9ee121571671ab263e18f314daa4e822"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a9ee121571671ab263e18f314daa4e822">XV_HDMIRX1_DBG_STA_WA_TAP_CHGALL_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:a9ee121571671ab263e18f314daa4e822"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Word aligner tap select changed all lanes mask.  <a href="#a9ee121571671ab263e18f314daa4e822">More...</a><br/></td></tr>
<tr class="separator:a9ee121571671ab263e18f314daa4e822"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad9f1648d81ac01691581f970b6a4ca02"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad9f1648d81ac01691581f970b6a4ca02">XV_HDMIRX1_DBG_STA_WA_TAP_CHG0_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:ad9f1648d81ac01691581f970b6a4ca02"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word aligner tap select changed lane 0 mask.  <a href="#ad9f1648d81ac01691581f970b6a4ca02">More...</a><br/></td></tr>
<tr class="separator:ad9f1648d81ac01691581f970b6a4ca02"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6cde27a94c44a2f4ada850cda21bf996"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a6cde27a94c44a2f4ada850cda21bf996">XV_HDMIRX1_DBG_STA_WA_TAP_CHG1_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a6cde27a94c44a2f4ada850cda21bf996"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word aligner tap select changed lane 1 mask.  <a href="#a6cde27a94c44a2f4ada850cda21bf996">More...</a><br/></td></tr>
<tr class="separator:a6cde27a94c44a2f4ada850cda21bf996"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7c80e7c6a06c1c6c1e37ba34bd559736"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7c80e7c6a06c1c6c1e37ba34bd559736">XV_HDMIRX1_DBG_STA_WA_TAP_CHG2_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a7c80e7c6a06c1c6c1e37ba34bd559736"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word aligner tap select changed lane 2 mask.  <a href="#a7c80e7c6a06c1c6c1e37ba34bd559736">More...</a><br/></td></tr>
<tr class="separator:a7c80e7c6a06c1c6c1e37ba34bd559736"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae4da0f552fe1f76b4301444c2e25ae36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae4da0f552fe1f76b4301444c2e25ae36">XV_HDMIRX1_DBG_STA_WA_TAP_CHG3_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:ae4da0f552fe1f76b4301444c2e25ae36"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Word aligner tap select changed lane 3 mask.  <a href="#ae4da0f552fe1f76b4301444c2e25ae36">More...</a><br/></td></tr>
<tr class="separator:ae4da0f552fe1f76b4301444c2e25ae36"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af2f364dc06424596ccc3ad6ab2b5e547"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af2f364dc06424596ccc3ad6ab2b5e547">XV_HDMIRX1_DBG_STA_WA_LOCK_CHGALL_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:af2f364dc06424596ccc3ad6ab2b5e547"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Word aligner tap select changed all lanes mask.  <a href="#af2f364dc06424596ccc3ad6ab2b5e547">More...</a><br/></td></tr>
<tr class="separator:af2f364dc06424596ccc3ad6ab2b5e547"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac99474f377d76e370d9dde2c72fac684"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac99474f377d76e370d9dde2c72fac684">XV_HDMIRX1_DBG_STA_WA_LOCK_CHGALL_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ac99474f377d76e370d9dde2c72fac684"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Word aligner tap select changed all lanes mask.  <a href="#ac99474f377d76e370d9dde2c72fac684">More...</a><br/></td></tr>
<tr class="separator:ac99474f377d76e370d9dde2c72fac684"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afabc42d9f5e367abca6bf7e82c4fcc9b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#afabc42d9f5e367abca6bf7e82c4fcc9b">XV_HDMIRX1_DBG_STA_WA_LOCK_CHG0_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:afabc42d9f5e367abca6bf7e82c4fcc9b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word aligner tap select changed lane 0 mask.  <a href="#afabc42d9f5e367abca6bf7e82c4fcc9b">More...</a><br/></td></tr>
<tr class="separator:afabc42d9f5e367abca6bf7e82c4fcc9b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae6c47612994744b602bbd9d3ec420474"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae6c47612994744b602bbd9d3ec420474">XV_HDMIRX1_DBG_STA_WA_LOCK_CHG1_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:ae6c47612994744b602bbd9d3ec420474"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word aligner tap select changed lane 1 mask.  <a href="#ae6c47612994744b602bbd9d3ec420474">More...</a><br/></td></tr>
<tr class="separator:ae6c47612994744b602bbd9d3ec420474"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa97364353f5889e64fdb0f2d79dbc87e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa97364353f5889e64fdb0f2d79dbc87e">XV_HDMIRX1_DBG_STA_WA_LOCK_CHG2_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:aa97364353f5889e64fdb0f2d79dbc87e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word aligner tap select changed lane 2 mask.  <a href="#aa97364353f5889e64fdb0f2d79dbc87e">More...</a><br/></td></tr>
<tr class="separator:aa97364353f5889e64fdb0f2d79dbc87e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0c90cd98ac9cd239267827bfe5342770"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a0c90cd98ac9cd239267827bfe5342770">XV_HDMIRX1_DBG_STA_WA_LOCK_CHG3_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:a0c90cd98ac9cd239267827bfe5342770"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Word aligner tap select changed lane 3 mask.  <a href="#a0c90cd98ac9cd239267827bfe5342770">More...</a><br/></td></tr>
<tr class="separator:a0c90cd98ac9cd239267827bfe5342770"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae71ca916fc1e751c0f5721bade5ab3b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae71ca916fc1e751c0f5721bade5ab3b6">XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHGALL_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:ae71ca916fc1e751c0f5721bade5ab3b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Word aligner tap select changed all lanes mask.  <a href="#ae71ca916fc1e751c0f5721bade5ab3b6">More...</a><br/></td></tr>
<tr class="separator:ae71ca916fc1e751c0f5721bade5ab3b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3d000d222218f9abca8a2dabd6626936"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a3d000d222218f9abca8a2dabd6626936">XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHGALL_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a3d000d222218f9abca8a2dabd6626936"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Word aligner tap select changed all lanes mask.  <a href="#a3d000d222218f9abca8a2dabd6626936">More...</a><br/></td></tr>
<tr class="separator:a3d000d222218f9abca8a2dabd6626936"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad22edcce4ae3218c3f636eb90a64638b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad22edcce4ae3218c3f636eb90a64638b">XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHG0_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:ad22edcce4ae3218c3f636eb90a64638b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word aligner tap select changed lane 0 mask.  <a href="#ad22edcce4ae3218c3f636eb90a64638b">More...</a><br/></td></tr>
<tr class="separator:ad22edcce4ae3218c3f636eb90a64638b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad19b9ec98349945260a33d590ed82b8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad19b9ec98349945260a33d590ed82b8b">XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHG1_MASK</a>&#160;&#160;&#160;(1&lt;&lt;9)</td></tr>
<tr class="memdesc:ad19b9ec98349945260a33d590ed82b8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word aligner tap select changed lane 1 mask.  <a href="#ad19b9ec98349945260a33d590ed82b8b">More...</a><br/></td></tr>
<tr class="separator:ad19b9ec98349945260a33d590ed82b8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a010c0a848e4f8bcee9abea98663922c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a010c0a848e4f8bcee9abea98663922c1">XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHG2_MASK</a>&#160;&#160;&#160;(1&lt;&lt;10)</td></tr>
<tr class="memdesc:a010c0a848e4f8bcee9abea98663922c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word aligner tap select changed lane 2 mask.  <a href="#a010c0a848e4f8bcee9abea98663922c1">More...</a><br/></td></tr>
<tr class="separator:a010c0a848e4f8bcee9abea98663922c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab31ae65332d2db183a0a22b71fad3551"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab31ae65332d2db183a0a22b71fad3551">XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHG3_MASK</a>&#160;&#160;&#160;(1&lt;&lt;11)</td></tr>
<tr class="memdesc:ab31ae65332d2db183a0a22b71fad3551"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Word aligner tap select changed lane 3 mask.  <a href="#ab31ae65332d2db183a0a22b71fad3551">More...</a><br/></td></tr>
<tr class="separator:ab31ae65332d2db183a0a22b71fad3551"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9db246d6864fa36907e4328865361617"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a9db246d6864fa36907e4328865361617">XV_HDMIRX1_DBG_STA_LANE_LOCK_CHGALL_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:a9db246d6864fa36907e4328865361617"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Word aligner tap select changed all lanes mask.  <a href="#a9db246d6864fa36907e4328865361617">More...</a><br/></td></tr>
<tr class="separator:a9db246d6864fa36907e4328865361617"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a01fb2daa2e91e2578d672460d8e76a31"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a01fb2daa2e91e2578d672460d8e76a31">XV_HDMIRX1_DBG_STA_LANE_LOCK_CHGALL_SHIFT</a>&#160;&#160;&#160;12</td></tr>
<tr class="memdesc:a01fb2daa2e91e2578d672460d8e76a31"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Word aligner tap select changed all lanes mask.  <a href="#a01fb2daa2e91e2578d672460d8e76a31">More...</a><br/></td></tr>
<tr class="separator:a01fb2daa2e91e2578d672460d8e76a31"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abadc9136ced82249f70e07e254289521"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#abadc9136ced82249f70e07e254289521">XV_HDMIRX1_DBG_STA_LANE_LOCK_CHG0_MASK</a>&#160;&#160;&#160;(1&lt;&lt;12)</td></tr>
<tr class="memdesc:abadc9136ced82249f70e07e254289521"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word aligner tap select changed lane 0 mask.  <a href="#abadc9136ced82249f70e07e254289521">More...</a><br/></td></tr>
<tr class="separator:abadc9136ced82249f70e07e254289521"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a94dc312749fdf9a840aede23f3800544"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a94dc312749fdf9a840aede23f3800544">XV_HDMIRX1_DBG_STA_LANE_LOCK_CHG1_MASK</a>&#160;&#160;&#160;(1&lt;&lt;13)</td></tr>
<tr class="memdesc:a94dc312749fdf9a840aede23f3800544"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word aligner tap select changed lane 1 mask.  <a href="#a94dc312749fdf9a840aede23f3800544">More...</a><br/></td></tr>
<tr class="separator:a94dc312749fdf9a840aede23f3800544"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a285820aa856b28b4cdaf13ac2f9b66b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a285820aa856b28b4cdaf13ac2f9b66b5">XV_HDMIRX1_DBG_STA_LANE_LOCK_CHG2_MASK</a>&#160;&#160;&#160;(1&lt;&lt;14)</td></tr>
<tr class="memdesc:a285820aa856b28b4cdaf13ac2f9b66b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word aligner tap select changed lane 2 mask.  <a href="#a285820aa856b28b4cdaf13ac2f9b66b5">More...</a><br/></td></tr>
<tr class="separator:a285820aa856b28b4cdaf13ac2f9b66b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a366da1bd6d5beb7e7b588cc7f032c984"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a366da1bd6d5beb7e7b588cc7f032c984">XV_HDMIRX1_DBG_STA_LANE_LOCK_CHG3_MASK</a>&#160;&#160;&#160;(1&lt;&lt;15)</td></tr>
<tr class="memdesc:a366da1bd6d5beb7e7b588cc7f032c984"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Word aligner tap select changed lane 3 mask.  <a href="#a366da1bd6d5beb7e7b588cc7f032c984">More...</a><br/></td></tr>
<tr class="separator:a366da1bd6d5beb7e7b588cc7f032c984"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aceb903127dc18e063143a5e9a63b1757"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aceb903127dc18e063143a5e9a63b1757">XV_HDMIRX1_DBG_STA_SKEW_LOCK_CHG_MASK</a>&#160;&#160;&#160;(1&lt;&lt;16)</td></tr>
<tr class="memdesc:aceb903127dc18e063143a5e9a63b1757"><td class="mdescLeft">&#160;</td><td class="mdescRight">Word aligner tap select changed lane 0 mask.  <a href="#aceb903127dc18e063143a5e9a63b1757">More...</a><br/></td></tr>
<tr class="separator:aceb903127dc18e063143a5e9a63b1757"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af194c444b1a273aed3950eca10ca1135"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af194c444b1a273aed3950eca10ca1135">XV_HDMIRX1_PIO_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(0*4))</td></tr>
<tr class="memdesc:af194c444b1a273aed3950eca10ca1135"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Identification register offset.  <a href="#af194c444b1a273aed3950eca10ca1135">More...</a><br/></td></tr>
<tr class="separator:af194c444b1a273aed3950eca10ca1135"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aad8520194df2924611a96f965a5f57c6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aad8520194df2924611a96f965a5f57c6">XV_HDMIRX1_PIO_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(1*4))</td></tr>
<tr class="memdesc:aad8520194df2924611a96f965a5f57c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control register offset.  <a href="#aad8520194df2924611a96f965a5f57c6">More...</a><br/></td></tr>
<tr class="separator:aad8520194df2924611a96f965a5f57c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aad7f2e6a3f83a5b545340458f0d696ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aad7f2e6a3f83a5b545340458f0d696ca">XV_HDMIRX1_PIO_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(2*4))</td></tr>
<tr class="memdesc:aad7f2e6a3f83a5b545340458f0d696ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Register Set offset.  <a href="#aad7f2e6a3f83a5b545340458f0d696ca">More...</a><br/></td></tr>
<tr class="separator:aad7f2e6a3f83a5b545340458f0d696ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab783565a557552b6340347c74fa21ad9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab783565a557552b6340347c74fa21ad9">XV_HDMIRX1_PIO_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(3*4))</td></tr>
<tr class="memdesc:ab783565a557552b6340347c74fa21ad9"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Register Clear offset.  <a href="#ab783565a557552b6340347c74fa21ad9">More...</a><br/></td></tr>
<tr class="separator:ab783565a557552b6340347c74fa21ad9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a010800518b582144dfb9dcc66525faf6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a010800518b582144dfb9dcc66525faf6">XV_HDMIRX1_PIO_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(4*4))</td></tr>
<tr class="memdesc:a010800518b582144dfb9dcc66525faf6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Status Register offset.  <a href="#a010800518b582144dfb9dcc66525faf6">More...</a><br/></td></tr>
<tr class="separator:a010800518b582144dfb9dcc66525faf6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2762aba9d45253971668c25e35400e3f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a2762aba9d45253971668c25e35400e3f">XV_HDMIRX1_PIO_OUT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(5*4))</td></tr>
<tr class="memdesc:a2762aba9d45253971668c25e35400e3f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Register offset.  <a href="#a2762aba9d45253971668c25e35400e3f">More...</a><br/></td></tr>
<tr class="separator:a2762aba9d45253971668c25e35400e3f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ada35683dde8266cadc45f975707d577b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ada35683dde8266cadc45f975707d577b">XV_HDMIRX1_PIO_OUT_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(6*4))</td></tr>
<tr class="memdesc:ada35683dde8266cadc45f975707d577b"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Register Set offset.  <a href="#ada35683dde8266cadc45f975707d577b">More...</a><br/></td></tr>
<tr class="separator:ada35683dde8266cadc45f975707d577b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9f3ee5ffefea5fea81b6278347ac0911"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a9f3ee5ffefea5fea81b6278347ac0911">XV_HDMIRX1_PIO_OUT_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(7*4))</td></tr>
<tr class="memdesc:a9f3ee5ffefea5fea81b6278347ac0911"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Register Clear offset.  <a href="#a9f3ee5ffefea5fea81b6278347ac0911">More...</a><br/></td></tr>
<tr class="separator:a9f3ee5ffefea5fea81b6278347ac0911"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acdedab9c5aa955316fd71fcf8597ba83"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#acdedab9c5aa955316fd71fcf8597ba83">XV_HDMIRX1_PIO_OUT_MSK_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(8*4))</td></tr>
<tr class="memdesc:acdedab9c5aa955316fd71fcf8597ba83"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Mask Register offset.  <a href="#acdedab9c5aa955316fd71fcf8597ba83">More...</a><br/></td></tr>
<tr class="separator:acdedab9c5aa955316fd71fcf8597ba83"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a49992379740fbcb1480c2ea6aa8709c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a49992379740fbcb1480c2ea6aa8709c2">XV_HDMIRX1_PIO_IN_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(9*4))</td></tr>
<tr class="memdesc:a49992379740fbcb1480c2ea6aa8709c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Register offset.  <a href="#a49992379740fbcb1480c2ea6aa8709c2">More...</a><br/></td></tr>
<tr class="separator:a49992379740fbcb1480c2ea6aa8709c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1b566a2b83360e0a9712dec14f7d19a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1b566a2b83360e0a9712dec14f7d19a3">XV_HDMIRX1_PIO_IN_EVT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(10*4))</td></tr>
<tr class="memdesc:a1b566a2b83360e0a9712dec14f7d19a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Event Register offset.  <a href="#a1b566a2b83360e0a9712dec14f7d19a3">More...</a><br/></td></tr>
<tr class="separator:a1b566a2b83360e0a9712dec14f7d19a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0560f28ec4c56a00c8922c127fabcbee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a0560f28ec4c56a00c8922c127fabcbee">XV_HDMIRX1_PIO_IN_EVT_RE_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(11*4))</td></tr>
<tr class="memdesc:a0560f28ec4c56a00c8922c127fabcbee"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Event Rising Edge Register offset.  <a href="#a0560f28ec4c56a00c8922c127fabcbee">More...</a><br/></td></tr>
<tr class="separator:a0560f28ec4c56a00c8922c127fabcbee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a84f86b84d6ad904b4c48821aacd45533"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a84f86b84d6ad904b4c48821aacd45533">XV_HDMIRX1_PIO_IN_EVT_FE_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(12*4))</td></tr>
<tr class="memdesc:a84f86b84d6ad904b4c48821aacd45533"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Event Falling Edge Register offset.  <a href="#a84f86b84d6ad904b4c48821aacd45533">More...</a><br/></td></tr>
<tr class="separator:a84f86b84d6ad904b4c48821aacd45533"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab52074178b6019af2335dc97d5a39548"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab52074178b6019af2335dc97d5a39548">XV_HDMIRX1_DSC_CVTEM_HSYNC_HFRONT</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(13*4))</td></tr>
<tr class="memdesc:ab52074178b6019af2335dc97d5a39548"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original HFront and Hsync values.  <a href="#ab52074178b6019af2335dc97d5a39548">More...</a><br/></td></tr>
<tr class="separator:ab52074178b6019af2335dc97d5a39548"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3ab5339b2298e63b0a1ea9adf9552a8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a3ab5339b2298e63b0a1ea9adf9552a8b">XV_HDMIRX1_DSC_CVTEM_HBACK_HCACT</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(14*4))</td></tr>
<tr class="memdesc:a3ab5339b2298e63b0a1ea9adf9552a8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original HBack and HCActive values.  <a href="#a3ab5339b2298e63b0a1ea9adf9552a8b">More...</a><br/></td></tr>
<tr class="separator:a3ab5339b2298e63b0a1ea9adf9552a8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7c7f0137214f7980b048526507b4d41a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7c7f0137214f7980b048526507b4d41a">XV_HDMIRX1_DSC_CVTEM_HACT_VACT</a>&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(15*4))</td></tr>
<tr class="memdesc:a7c7f0137214f7980b048526507b4d41a"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original HActive and VActive values.  <a href="#a7c7f0137214f7980b048526507b4d41a">More...</a><br/></td></tr>
<tr class="separator:a7c7f0137214f7980b048526507b4d41a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9ba54758033579b93394c923fa15dceb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a9ba54758033579b93394c923fa15dceb">XV_HDMIRX1_PIO_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a9ba54758033579b93394c923fa15dceb"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Run mask.  <a href="#a9ba54758033579b93394c923fa15dceb">More...</a><br/></td></tr>
<tr class="separator:a9ba54758033579b93394c923fa15dceb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab295c07286c024627e6b5dd1abc99451"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab295c07286c024627e6b5dd1abc99451">XV_HDMIRX1_PIO_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:ab295c07286c024627e6b5dd1abc99451"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Interrupt Enable mask.  <a href="#ab295c07286c024627e6b5dd1abc99451">More...</a><br/></td></tr>
<tr class="separator:ab295c07286c024627e6b5dd1abc99451"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0d4a80745016667fabf3927fb58bc835"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a0d4a80745016667fabf3927fb58bc835">XV_HDMIRX1_PIO_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a0d4a80745016667fabf3927fb58bc835"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Status Interrupt mask.  <a href="#a0d4a80745016667fabf3927fb58bc835">More...</a><br/></td></tr>
<tr class="separator:a0d4a80745016667fabf3927fb58bc835"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aef8c2bdce4282861650f4b2c24b4bf58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aef8c2bdce4282861650f4b2c24b4bf58">XV_HDMIRX1_PIO_STA_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:aef8c2bdce4282861650f4b2c24b4bf58"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Status Event mask.  <a href="#aef8c2bdce4282861650f4b2c24b4bf58">More...</a><br/></td></tr>
<tr class="separator:aef8c2bdce4282861650f4b2c24b4bf58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aca9ae5b99ad8d51e238bd4837a8cc2da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aca9ae5b99ad8d51e238bd4837a8cc2da">XV_HDMIRX1_PIO_OUT_RESET_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:aca9ae5b99ad8d51e238bd4837a8cc2da"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Reset mask.  <a href="#aca9ae5b99ad8d51e238bd4837a8cc2da">More...</a><br/></td></tr>
<tr class="separator:aca9ae5b99ad8d51e238bd4837a8cc2da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9664bc1a8eba4759abae05a526070145"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a9664bc1a8eba4759abae05a526070145">XV_HDMIRX1_PIO_OUT_LNK_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a9664bc1a8eba4759abae05a526070145"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out video enable mask.  <a href="#a9664bc1a8eba4759abae05a526070145">More...</a><br/></td></tr>
<tr class="separator:a9664bc1a8eba4759abae05a526070145"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a519c487569199868a3cb9e63ca31c741"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a519c487569199868a3cb9e63ca31c741">XV_HDMIRX1_PIO_OUT_VID_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a519c487569199868a3cb9e63ca31c741"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out video enable mask.  <a href="#a519c487569199868a3cb9e63ca31c741">More...</a><br/></td></tr>
<tr class="separator:a519c487569199868a3cb9e63ca31c741"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad0879431e9c01049409338523d61c179"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad0879431e9c01049409338523d61c179">XV_HDMIRX1_PIO_OUT_HPD_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:ad0879431e9c01049409338523d61c179"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Hot-Plug Detect mask.  <a href="#ad0879431e9c01049409338523d61c179">More...</a><br/></td></tr>
<tr class="separator:ad0879431e9c01049409338523d61c179"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a452a30d01e4984cc21070aeed8440edb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a452a30d01e4984cc21070aeed8440edb">XV_HDMIRX1_PIO_OUT_DEEP_COLOR_MASK</a>&#160;&#160;&#160;0x30</td></tr>
<tr class="memdesc:a452a30d01e4984cc21070aeed8440edb"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Deep Color mask.  <a href="#a452a30d01e4984cc21070aeed8440edb">More...</a><br/></td></tr>
<tr class="separator:a452a30d01e4984cc21070aeed8440edb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a478987cdc818e2083db0f500ef6b66ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a478987cdc818e2083db0f500ef6b66ab">XV_HDMIRX1_PIO_OUT_PIXEL_RATE_MASK</a>&#160;&#160;&#160;0xC0</td></tr>
<tr class="memdesc:a478987cdc818e2083db0f500ef6b66ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Pixel Rate mask.  <a href="#a478987cdc818e2083db0f500ef6b66ab">More...</a><br/></td></tr>
<tr class="separator:a478987cdc818e2083db0f500ef6b66ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acb55268d76c753b98f3b5d991f0cb5a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#acb55268d76c753b98f3b5d991f0cb5a0">XV_HDMIRX1_PIO_OUT_SAMPLE_RATE_MASK</a>&#160;&#160;&#160;0x300</td></tr>
<tr class="memdesc:acb55268d76c753b98f3b5d991f0cb5a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Sample Rate mask.  <a href="#acb55268d76c753b98f3b5d991f0cb5a0">More...</a><br/></td></tr>
<tr class="separator:acb55268d76c753b98f3b5d991f0cb5a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a686038ae877f6ad613ca1eb8d6e20596"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a686038ae877f6ad613ca1eb8d6e20596">XV_HDMIRX1_PIO_OUT_COLOR_SPACE_MASK</a>&#160;&#160;&#160;0xC00</td></tr>
<tr class="memdesc:a686038ae877f6ad613ca1eb8d6e20596"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Color Space mask.  <a href="#a686038ae877f6ad613ca1eb8d6e20596">More...</a><br/></td></tr>
<tr class="separator:a686038ae877f6ad613ca1eb8d6e20596"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a40633ba82555b5031c1d8fcce419bf3e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a40633ba82555b5031c1d8fcce419bf3e">XV_HDMIRX1_PIO_OUT_PP_MASK</a>&#160;&#160;&#160;0x70000</td></tr>
<tr class="memdesc:a40633ba82555b5031c1d8fcce419bf3e"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Pixel Phase mask.  <a href="#a40633ba82555b5031c1d8fcce419bf3e">More...</a><br/></td></tr>
<tr class="separator:a40633ba82555b5031c1d8fcce419bf3e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab7fa4573aef8cdef877bb782670b5dd2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab7fa4573aef8cdef877bb782670b5dd2">XV_HDMIRX1_PIO_OUT_AXIS_EN_MASK</a>&#160;&#160;&#160;0x80000</td></tr>
<tr class="memdesc:ab7fa4573aef8cdef877bb782670b5dd2"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Axis Enable mask.  <a href="#ab7fa4573aef8cdef877bb782670b5dd2">More...</a><br/></td></tr>
<tr class="separator:ab7fa4573aef8cdef877bb782670b5dd2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6a6ba1381257dd1757b5296d1482a14b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a6a6ba1381257dd1757b5296d1482a14b">XV_HDMIRX1_PIO_OUT_DEEP_COLOR_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:a6a6ba1381257dd1757b5296d1482a14b"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Deep Color shift.  <a href="#a6a6ba1381257dd1757b5296d1482a14b">More...</a><br/></td></tr>
<tr class="separator:a6a6ba1381257dd1757b5296d1482a14b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3177edd91ed0cd44227a908abcd854ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a3177edd91ed0cd44227a908abcd854ca">XV_HDMIRX1_PIO_OUT_PIXEL_RATE_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:a3177edd91ed0cd44227a908abcd854ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Pixel Rate Shift.  <a href="#a3177edd91ed0cd44227a908abcd854ca">More...</a><br/></td></tr>
<tr class="separator:a3177edd91ed0cd44227a908abcd854ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7aa254b975a393b0e6b1b05026fb2e13"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7aa254b975a393b0e6b1b05026fb2e13">XV_HDMIRX1_PIO_OUT_SAMPLE_RATE_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a7aa254b975a393b0e6b1b05026fb2e13"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Sample Rate shift.  <a href="#a7aa254b975a393b0e6b1b05026fb2e13">More...</a><br/></td></tr>
<tr class="separator:a7aa254b975a393b0e6b1b05026fb2e13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab91524f2e3868ea812c5e9a6e6a877ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab91524f2e3868ea812c5e9a6e6a877ec">XV_HDMIRX1_PIO_OUT_COLOR_SPACE_SHIFT</a>&#160;&#160;&#160;10</td></tr>
<tr class="memdesc:ab91524f2e3868ea812c5e9a6e6a877ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Color Space shift.  <a href="#ab91524f2e3868ea812c5e9a6e6a877ec">More...</a><br/></td></tr>
<tr class="separator:ab91524f2e3868ea812c5e9a6e6a877ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a562f10222f58d4c0debc2227ef9b8247"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a562f10222f58d4c0debc2227ef9b8247">XV_HDMIRX1_PIO_OUT_PP_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a562f10222f58d4c0debc2227ef9b8247"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Pixel Phase shift.  <a href="#a562f10222f58d4c0debc2227ef9b8247">More...</a><br/></td></tr>
<tr class="separator:a562f10222f58d4c0debc2227ef9b8247"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a373757bf8fb4bca95302a14fc014a878"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a373757bf8fb4bca95302a14fc014a878">XV_HDMIRX1_PIO_OUT_SCRM_MASK</a>&#160;&#160;&#160;(1&lt;&lt;12)</td></tr>
<tr class="memdesc:a373757bf8fb4bca95302a14fc014a878"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Scrambler mask.  <a href="#a373757bf8fb4bca95302a14fc014a878">More...</a><br/></td></tr>
<tr class="separator:a373757bf8fb4bca95302a14fc014a878"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af5b360bef2825b063ec1d6a4f5cfe55a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af5b360bef2825b063ec1d6a4f5cfe55a">XV_HDMIRX1_PIO_OUT_BRIDGE_YUV420_MASK</a>&#160;&#160;&#160;(1&lt;&lt;29)</td></tr>
<tr class="memdesc:af5b360bef2825b063ec1d6a4f5cfe55a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Bridge_YUV420 mask.  <a href="#af5b360bef2825b063ec1d6a4f5cfe55a">More...</a><br/></td></tr>
<tr class="separator:af5b360bef2825b063ec1d6a4f5cfe55a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab38c46f5b81c2bfd313314921cf5c275"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab38c46f5b81c2bfd313314921cf5c275">XV_HDMIRX1_PIO_OUT_BRIDGE_PIXEL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;30)</td></tr>
<tr class="memdesc:ab38c46f5b81c2bfd313314921cf5c275"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Bridge_Pixel drop mask.  <a href="#ab38c46f5b81c2bfd313314921cf5c275">More...</a><br/></td></tr>
<tr class="separator:ab38c46f5b81c2bfd313314921cf5c275"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a12d07ceb2b0cf661463eace18d19b370"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a12d07ceb2b0cf661463eace18d19b370">XV_HDMIRX1_PIO_OUT_INT_VRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a12d07ceb2b0cf661463eace18d19b370"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out INT_VRST mask.  <a href="#a12d07ceb2b0cf661463eace18d19b370">More...</a><br/></td></tr>
<tr class="separator:a12d07ceb2b0cf661463eace18d19b370"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a40d80538fcb5bc6ae4dd18590766b12c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a40d80538fcb5bc6ae4dd18590766b12c">XV_HDMIRX1_PIO_OUT_INT_LRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;20)</td></tr>
<tr class="memdesc:a40d80538fcb5bc6ae4dd18590766b12c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out INT_LRST mask.  <a href="#a40d80538fcb5bc6ae4dd18590766b12c">More...</a><br/></td></tr>
<tr class="separator:a40d80538fcb5bc6ae4dd18590766b12c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a67959c83fa1faaaccb685a9070cec447"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a67959c83fa1faaaccb685a9070cec447">XV_HDMIRX1_PIO_OUT_EXT_VRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;21)</td></tr>
<tr class="memdesc:a67959c83fa1faaaccb685a9070cec447"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out EXT_VRST mask.  <a href="#a67959c83fa1faaaccb685a9070cec447">More...</a><br/></td></tr>
<tr class="separator:a67959c83fa1faaaccb685a9070cec447"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af4e73625cd9540a0f4885dd41afd95eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af4e73625cd9540a0f4885dd41afd95eb">XV_HDMIRX1_PIO_OUT_EXT_SYSRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;22)</td></tr>
<tr class="memdesc:af4e73625cd9540a0f4885dd41afd95eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out EXT_SYSRST mask.  <a href="#af4e73625cd9540a0f4885dd41afd95eb">More...</a><br/></td></tr>
<tr class="separator:af4e73625cd9540a0f4885dd41afd95eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7e60d62918e48ee2e27bfc0064d3863d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7e60d62918e48ee2e27bfc0064d3863d">XV_HDMIRX1_PIO_OUT_DYN_HDR_DM_EN_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; 23)</td></tr>
<tr class="memdesc:a7e60d62918e48ee2e27bfc0064d3863d"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Dynamic HDR Data Mover enable mask.  <a href="#a7e60d62918e48ee2e27bfc0064d3863d">More...</a><br/></td></tr>
<tr class="separator:a7e60d62918e48ee2e27bfc0064d3863d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a106ccba962224187a330b068ddd772c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a106ccba962224187a330b068ddd772c1">XV_HDMIRX1_PIO_IN_DET_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a106ccba962224187a330b068ddd772c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In cable detect mask.  <a href="#a106ccba962224187a330b068ddd772c1">More...</a><br/></td></tr>
<tr class="separator:a106ccba962224187a330b068ddd772c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4ac3277902c44edfcce1cc6c8afcf2e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a4ac3277902c44edfcce1cc6c8afcf2e3">XV_HDMIRX1_PIO_IN_LNK_RDY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a4ac3277902c44edfcce1cc6c8afcf2e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In link ready mask.  <a href="#a4ac3277902c44edfcce1cc6c8afcf2e3">More...</a><br/></td></tr>
<tr class="separator:a4ac3277902c44edfcce1cc6c8afcf2e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7e39e0c95a43c2962ee66c1a45f3fbed"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7e39e0c95a43c2962ee66c1a45f3fbed">XV_HDMIRX1_PIO_IN_VID_RDY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a7e39e0c95a43c2962ee66c1a45f3fbed"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In video ready mask.  <a href="#a7e39e0c95a43c2962ee66c1a45f3fbed">More...</a><br/></td></tr>
<tr class="separator:a7e39e0c95a43c2962ee66c1a45f3fbed"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9e9029db2aff750b7c208c8eca7faff9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a9e9029db2aff750b7c208c8eca7faff9">XV_HDMIRX1_PIO_IN_MODE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a9e9029db2aff750b7c208c8eca7faff9"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Mode mask.  <a href="#a9e9029db2aff750b7c208c8eca7faff9">More...</a><br/></td></tr>
<tr class="separator:a9e9029db2aff750b7c208c8eca7faff9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7d01e744c692ff9a143309dd407196a9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7d01e744c692ff9a143309dd407196a9">XV_HDMIRX1_PIO_IN_SCRAMBLER_LOCKALLL_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:a7d01e744c692ff9a143309dd407196a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Scrambler lock all lanes mask.  <a href="#a7d01e744c692ff9a143309dd407196a9">More...</a><br/></td></tr>
<tr class="separator:a7d01e744c692ff9a143309dd407196a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afbf01122ade2aaaf05f758fb22095341"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#afbf01122ade2aaaf05f758fb22095341">XV_HDMIRX1_PIO_IN_SCRAMBLER_LOCKALLL_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:afbf01122ade2aaaf05f758fb22095341"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Scrambler lock all lanes shift.  <a href="#afbf01122ade2aaaf05f758fb22095341">More...</a><br/></td></tr>
<tr class="separator:afbf01122ade2aaaf05f758fb22095341"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afd4fb120b78254f2d9c8d7291f6854f2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#afd4fb120b78254f2d9c8d7291f6854f2">XV_HDMIRX1_PIO_IN_SCRAMBLER_LOCK0_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:afd4fb120b78254f2d9c8d7291f6854f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Scrambler lock 0 mask.  <a href="#afd4fb120b78254f2d9c8d7291f6854f2">More...</a><br/></td></tr>
<tr class="separator:afd4fb120b78254f2d9c8d7291f6854f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7ff42e4cf86eae3a34b4d1f708be8902"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7ff42e4cf86eae3a34b4d1f708be8902">XV_HDMIRX1_PIO_IN_SCRAMBLER_LOCK1_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:a7ff42e4cf86eae3a34b4d1f708be8902"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Scrambler lock 1 mask.  <a href="#a7ff42e4cf86eae3a34b4d1f708be8902">More...</a><br/></td></tr>
<tr class="separator:a7ff42e4cf86eae3a34b4d1f708be8902"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4d492282755dc2c57fa68144da30f2d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a4d492282755dc2c57fa68144da30f2d9">XV_HDMIRX1_PIO_IN_SCRAMBLER_LOCK2_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:a4d492282755dc2c57fa68144da30f2d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Scrambler lock 2 mask.  <a href="#a4d492282755dc2c57fa68144da30f2d9">More...</a><br/></td></tr>
<tr class="separator:a4d492282755dc2c57fa68144da30f2d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac0cdb812388d2c6c671cc5e884eed62f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac0cdb812388d2c6c671cc5e884eed62f">XV_HDMIRX1_PIO_IN_SCDC_SCRAMBLER_ENABLE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:ac0cdb812388d2c6c671cc5e884eed62f"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In SCDC scrambler enable mask.  <a href="#ac0cdb812388d2c6c671cc5e884eed62f">More...</a><br/></td></tr>
<tr class="separator:ac0cdb812388d2c6c671cc5e884eed62f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a51d2852cd78f9a896e224454b97f092b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a51d2852cd78f9a896e224454b97f092b">XV_HDMIRX1_PIO_IN_SCDC_TMDS_CLOCK_RATIO_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:a51d2852cd78f9a896e224454b97f092b"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In SCDC TMDS clock ratio mask.  <a href="#a51d2852cd78f9a896e224454b97f092b">More...</a><br/></td></tr>
<tr class="separator:a51d2852cd78f9a896e224454b97f092b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af4dcda505ba0f225b5b8c9cb9a3c1389"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af4dcda505ba0f225b5b8c9cb9a3c1389">XV_HDMIRX1_PIO_IN_ALIGNER_LOCK_MASK</a>&#160;&#160;&#160;(1&lt;&lt;9)</td></tr>
<tr class="memdesc:af4dcda505ba0f225b5b8c9cb9a3c1389"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In alinger lock mask.  <a href="#af4dcda505ba0f225b5b8c9cb9a3c1389">More...</a><br/></td></tr>
<tr class="separator:af4dcda505ba0f225b5b8c9cb9a3c1389"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a04e11b499092095ce68d48fc3f40e04c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a04e11b499092095ce68d48fc3f40e04c">XV_HDMIRX1_PIO_IN_BRDG_OVERFLOW_MASK</a>&#160;&#160;&#160;(1&lt;&lt;10)</td></tr>
<tr class="memdesc:a04e11b499092095ce68d48fc3f40e04c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In bridge overflow mask.  <a href="#a04e11b499092095ce68d48fc3f40e04c">More...</a><br/></td></tr>
<tr class="separator:a04e11b499092095ce68d48fc3f40e04c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:add83a38ee29484b49b58d3557b78622e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#add83a38ee29484b49b58d3557b78622e">XV_HDMIRX1_PIO_IN_DSC_EN_STRM_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; 11)</td></tr>
<tr class="memdesc:add83a38ee29484b49b58d3557b78622e"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In DSC packets present in stream.  <a href="#add83a38ee29484b49b58d3557b78622e">More...</a><br/></td></tr>
<tr class="separator:add83a38ee29484b49b58d3557b78622e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5223536dada6b7c9610aea11ae7a190b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a5223536dada6b7c9610aea11ae7a190b">XV_HDMIRX1_PIO_IN_DSC_EN_STRM_CHG_EVT_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; 11)</td></tr>
<tr class="memdesc:a5223536dada6b7c9610aea11ae7a190b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This bit is present in PIO_IN_EVT reg only.  <a href="#a5223536dada6b7c9610aea11ae7a190b">More...</a><br/></td></tr>
<tr class="separator:a5223536dada6b7c9610aea11ae7a190b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad9a3ed590d3044b9978cdcd1a20abe06"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad9a3ed590d3044b9978cdcd1a20abe06">XV_HDMIRX1_PIO_IN_DSC_PPS_PKT_ERR_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; 12)</td></tr>
<tr class="memdesc:ad9a3ed590d3044b9978cdcd1a20abe06"><td class="mdescLeft">&#160;</td><td class="mdescRight">This bit is preset in PIO_IN_EVT reg only.  <a href="#ad9a3ed590d3044b9978cdcd1a20abe06">More...</a><br/></td></tr>
<tr class="separator:ad9a3ed590d3044b9978cdcd1a20abe06"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a43188468463b05a798f04ea6d1e64d70"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a43188468463b05a798f04ea6d1e64d70">XV_HDMIRX1_DSC_CVTEM_HSYNC_HFRONT_ORIG_HFRONT_MASK</a>&#160;&#160;&#160;(0xFFFF)</td></tr>
<tr class="memdesc:a43188468463b05a798f04ea6d1e64d70"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original HFRONT mask.  <a href="#a43188468463b05a798f04ea6d1e64d70">More...</a><br/></td></tr>
<tr class="separator:a43188468463b05a798f04ea6d1e64d70"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac98227d95f8c6e4aac730bc6619971c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac98227d95f8c6e4aac730bc6619971c5">XV_HDMIRX1_DSC_CVTEM_HSYNC_HFRONT_ORIG_HFRONT_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:ac98227d95f8c6e4aac730bc6619971c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original HFRONT shift.  <a href="#ac98227d95f8c6e4aac730bc6619971c5">More...</a><br/></td></tr>
<tr class="separator:ac98227d95f8c6e4aac730bc6619971c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5afaf9e25105faf9e47ade7293e3af96"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a5afaf9e25105faf9e47ade7293e3af96">XV_HDMIRX1_DSC_CVTEM_HSYNC_HFRONT_ORIG_HSYNC_MASK</a>&#160;&#160;&#160;(0xFFFF)</td></tr>
<tr class="memdesc:a5afaf9e25105faf9e47ade7293e3af96"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original HSYNC mask.  <a href="#a5afaf9e25105faf9e47ade7293e3af96">More...</a><br/></td></tr>
<tr class="separator:a5afaf9e25105faf9e47ade7293e3af96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a504f2e3dc05b5f97b3b8e154719b3736"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a504f2e3dc05b5f97b3b8e154719b3736">XV_HDMIRX1_DSC_CVTEM_HSYNC_HFRONT_ORIG_HSYNC_SHIFT</a>&#160;&#160;&#160;(16)</td></tr>
<tr class="memdesc:a504f2e3dc05b5f97b3b8e154719b3736"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original HSYNC shift.  <a href="#a504f2e3dc05b5f97b3b8e154719b3736">More...</a><br/></td></tr>
<tr class="separator:a504f2e3dc05b5f97b3b8e154719b3736"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a33ad59621cd66368588b48003676a562"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a33ad59621cd66368588b48003676a562">XV_HDMIRX1_DSC_CVTEM_HBACK_HCACT_HBACK_MASK</a>&#160;&#160;&#160;(0xFFFF)</td></tr>
<tr class="memdesc:a33ad59621cd66368588b48003676a562"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original HBACK mask.  <a href="#a33ad59621cd66368588b48003676a562">More...</a><br/></td></tr>
<tr class="separator:a33ad59621cd66368588b48003676a562"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa8636582f103f89563e2d8e2b0f312f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa8636582f103f89563e2d8e2b0f312f7">XV_HDMIRX1_DSC_CVTEM_HBACK_HCACT_HBACK_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:aa8636582f103f89563e2d8e2b0f312f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original HBACK shift.  <a href="#aa8636582f103f89563e2d8e2b0f312f7">More...</a><br/></td></tr>
<tr class="separator:aa8636582f103f89563e2d8e2b0f312f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a33673f267b7167e5bf1b9e89f73e9c58"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a33673f267b7167e5bf1b9e89f73e9c58">XV_HDMIRX1_DSC_CVTEM_HBACK_HCACT_HCACT_MASK</a>&#160;&#160;&#160;(0xFFFF)</td></tr>
<tr class="memdesc:a33673f267b7167e5bf1b9e89f73e9c58"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original HCACT mask.  <a href="#a33673f267b7167e5bf1b9e89f73e9c58">More...</a><br/></td></tr>
<tr class="separator:a33673f267b7167e5bf1b9e89f73e9c58"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a86a4d6c4205afaf33c74a624bba37357"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a86a4d6c4205afaf33c74a624bba37357">XV_HDMIRX1_DSC_CVTEM_HBACK_HCACT_HCACT_SHIFT</a>&#160;&#160;&#160;(16)</td></tr>
<tr class="memdesc:a86a4d6c4205afaf33c74a624bba37357"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original HCACT shift.  <a href="#a86a4d6c4205afaf33c74a624bba37357">More...</a><br/></td></tr>
<tr class="separator:a86a4d6c4205afaf33c74a624bba37357"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac26c395846b60a6eff3f40e84312bd2e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac26c395846b60a6eff3f40e84312bd2e">XV_HDMIRX1_DSC_CVTEM_HACT_VACT_HACT_MASK</a>&#160;&#160;&#160;(0xFFFF)</td></tr>
<tr class="memdesc:ac26c395846b60a6eff3f40e84312bd2e"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original HACT mask.  <a href="#ac26c395846b60a6eff3f40e84312bd2e">More...</a><br/></td></tr>
<tr class="separator:ac26c395846b60a6eff3f40e84312bd2e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a085af547fd0813ab2aab56ee19c6bbf5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a085af547fd0813ab2aab56ee19c6bbf5">XV_HDMIRX1_DSC_CVTEM_HACT_VACT_HACT_SHIFT</a>&#160;&#160;&#160;(16)</td></tr>
<tr class="memdesc:a085af547fd0813ab2aab56ee19c6bbf5"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original HACT shift.  <a href="#a085af547fd0813ab2aab56ee19c6bbf5">More...</a><br/></td></tr>
<tr class="separator:a085af547fd0813ab2aab56ee19c6bbf5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a25459919a144cf71e428109defb64432"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a25459919a144cf71e428109defb64432">XV_HDMIRX1_DSC_CVTEM_HACT_VACT_VACT_MASK</a>&#160;&#160;&#160;(0xFFFF)</td></tr>
<tr class="memdesc:a25459919a144cf71e428109defb64432"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original VACT mask.  <a href="#a25459919a144cf71e428109defb64432">More...</a><br/></td></tr>
<tr class="separator:a25459919a144cf71e428109defb64432"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa9639bfe3edbda964191fce99e0c6821"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa9639bfe3edbda964191fce99e0c6821">XV_HDMIRX1_DSC_CVTEM_HACT_VACT_VACT_SHIFT</a>&#160;&#160;&#160;(0)</td></tr>
<tr class="memdesc:aa9639bfe3edbda964191fce99e0c6821"><td class="mdescLeft">&#160;</td><td class="mdescRight">DSC original VACT shift.  <a href="#aa9639bfe3edbda964191fce99e0c6821">More...</a><br/></td></tr>
<tr class="separator:aa9639bfe3edbda964191fce99e0c6821"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a96e1c2a18841fcfcc91736e225ce603c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a96e1c2a18841fcfcc91736e225ce603c">XV_HDMIRX1_TMR_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(0*4))</td></tr>
<tr class="memdesc:a96e1c2a18841fcfcc91736e225ce603c"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Identification register offset.  <a href="#a96e1c2a18841fcfcc91736e225ce603c">More...</a><br/></td></tr>
<tr class="separator:a96e1c2a18841fcfcc91736e225ce603c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac12ef34573fbbdd3716faff94534dbdc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac12ef34573fbbdd3716faff94534dbdc">XV_HDMIRX1_TMR_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(1*4))</td></tr>
<tr class="memdesc:ac12ef34573fbbdd3716faff94534dbdc"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control register offset.  <a href="#ac12ef34573fbbdd3716faff94534dbdc">More...</a><br/></td></tr>
<tr class="separator:ac12ef34573fbbdd3716faff94534dbdc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3d6d8df87e3d66f70c7517431b791a10"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a3d6d8df87e3d66f70c7517431b791a10">XV_HDMIRX1_TMR_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(2*4))</td></tr>
<tr class="memdesc:a3d6d8df87e3d66f70c7517431b791a10"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control Register Set offset.  <a href="#a3d6d8df87e3d66f70c7517431b791a10">More...</a><br/></td></tr>
<tr class="separator:a3d6d8df87e3d66f70c7517431b791a10"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1cdf2bc260e7b4039352ef7cea5638b9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1cdf2bc260e7b4039352ef7cea5638b9">XV_HDMIRX1_TMR_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(3*4))</td></tr>
<tr class="memdesc:a1cdf2bc260e7b4039352ef7cea5638b9"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control Register Clear offset.  <a href="#a1cdf2bc260e7b4039352ef7cea5638b9">More...</a><br/></td></tr>
<tr class="separator:a1cdf2bc260e7b4039352ef7cea5638b9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4afca904429b1f2e882bea212effe1cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a4afca904429b1f2e882bea212effe1cf">XV_HDMIRX1_TMR_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(4*4))</td></tr>
<tr class="memdesc:a4afca904429b1f2e882bea212effe1cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Status Register offset.  <a href="#a4afca904429b1f2e882bea212effe1cf">More...</a><br/></td></tr>
<tr class="separator:a4afca904429b1f2e882bea212effe1cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a293fd830851198f7e914a854331b5896"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a293fd830851198f7e914a854331b5896">XV_HDMIRX1_TMR1_CNT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(5*4))</td></tr>
<tr class="memdesc:a293fd830851198f7e914a854331b5896"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Counter Register offset.  <a href="#a293fd830851198f7e914a854331b5896">More...</a><br/></td></tr>
<tr class="separator:a293fd830851198f7e914a854331b5896"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeae47d24687bc43e32160a9308182746"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aeae47d24687bc43e32160a9308182746">XV_HDMIRX1_TMR2_CNT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(6*4))</td></tr>
<tr class="memdesc:aeae47d24687bc43e32160a9308182746"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Counter Register offset.  <a href="#aeae47d24687bc43e32160a9308182746">More...</a><br/></td></tr>
<tr class="separator:aeae47d24687bc43e32160a9308182746"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae3314caa4470dc986d1d7a50f1de62c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae3314caa4470dc986d1d7a50f1de62c9">XV_HDMIRX1_TMR3_CNT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(7*4))</td></tr>
<tr class="memdesc:ae3314caa4470dc986d1d7a50f1de62c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Counter Register offset.  <a href="#ae3314caa4470dc986d1d7a50f1de62c9">More...</a><br/></td></tr>
<tr class="separator:ae3314caa4470dc986d1d7a50f1de62c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b45e7f59deb365e580565110ec1be4e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a2b45e7f59deb365e580565110ec1be4e">XV_HDMIRX1_TMR4_CNT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(8*4))</td></tr>
<tr class="memdesc:a2b45e7f59deb365e580565110ec1be4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Counter Register offset.  <a href="#a2b45e7f59deb365e580565110ec1be4e">More...</a><br/></td></tr>
<tr class="separator:a2b45e7f59deb365e580565110ec1be4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4971c7cbae30577c586eb34bddec2aac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a4971c7cbae30577c586eb34bddec2aac">XV_HDMIRX1_TMR1_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a4971c7cbae30577c586eb34bddec2aac"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control Run mask.  <a href="#a4971c7cbae30577c586eb34bddec2aac">More...</a><br/></td></tr>
<tr class="separator:a4971c7cbae30577c586eb34bddec2aac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac3f7fead56ecd78e386866c94c088e4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac3f7fead56ecd78e386866c94c088e4b">XV_HDMIRX1_TMR1_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:ac3f7fead56ecd78e386866c94c088e4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control Interrupt Enable mask.  <a href="#ac3f7fead56ecd78e386866c94c088e4b">More...</a><br/></td></tr>
<tr class="separator:ac3f7fead56ecd78e386866c94c088e4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2efd70def06239d90d9cfa77a554b478"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a2efd70def06239d90d9cfa77a554b478">XV_HDMIRX1_TMR2_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a2efd70def06239d90d9cfa77a554b478"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control Run mask.  <a href="#a2efd70def06239d90d9cfa77a554b478">More...</a><br/></td></tr>
<tr class="separator:a2efd70def06239d90d9cfa77a554b478"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab49a117151e93626b4c4e6cfaa88fbca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab49a117151e93626b4c4e6cfaa88fbca">XV_HDMIRX1_TMR2_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:ab49a117151e93626b4c4e6cfaa88fbca"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control Interrupt Enable mask.  <a href="#ab49a117151e93626b4c4e6cfaa88fbca">More...</a><br/></td></tr>
<tr class="separator:ab49a117151e93626b4c4e6cfaa88fbca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afeea10b36e6aae8f6924ff77a9f16989"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#afeea10b36e6aae8f6924ff77a9f16989">XV_HDMIRX1_TMR3_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:afeea10b36e6aae8f6924ff77a9f16989"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control Run mask.  <a href="#afeea10b36e6aae8f6924ff77a9f16989">More...</a><br/></td></tr>
<tr class="separator:afeea10b36e6aae8f6924ff77a9f16989"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa49f4509e6046355bfdd463e060bf81d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa49f4509e6046355bfdd463e060bf81d">XV_HDMIRX1_TMR3_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:aa49f4509e6046355bfdd463e060bf81d"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control Interrupt Enable mask.  <a href="#aa49f4509e6046355bfdd463e060bf81d">More...</a><br/></td></tr>
<tr class="separator:aa49f4509e6046355bfdd463e060bf81d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a404594f6834c97a323eccb1f6acf10e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a404594f6834c97a323eccb1f6acf10e4">XV_HDMIRX1_TMR4_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:a404594f6834c97a323eccb1f6acf10e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control Run mask.  <a href="#a404594f6834c97a323eccb1f6acf10e4">More...</a><br/></td></tr>
<tr class="separator:a404594f6834c97a323eccb1f6acf10e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad4ccd558833c924e452e41b04f4aad67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad4ccd558833c924e452e41b04f4aad67">XV_HDMIRX1_TMR4_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:ad4ccd558833c924e452e41b04f4aad67"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Control Interrupt Enable mask.  <a href="#ad4ccd558833c924e452e41b04f4aad67">More...</a><br/></td></tr>
<tr class="separator:ad4ccd558833c924e452e41b04f4aad67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af91d2f9f96e679cac7647029f58ec4f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af91d2f9f96e679cac7647029f58ec4f7">XV_HDMIRX1_TMR_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:af91d2f9f96e679cac7647029f58ec4f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Status Interrupt mask.  <a href="#af91d2f9f96e679cac7647029f58ec4f7">More...</a><br/></td></tr>
<tr class="separator:af91d2f9f96e679cac7647029f58ec4f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8540999b4f1e41b762f357cc838e5584"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a8540999b4f1e41b762f357cc838e5584">XV_HDMIRX1_TMR1_STA_CNT_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a8540999b4f1e41b762f357cc838e5584"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Status counter Event mask.  <a href="#a8540999b4f1e41b762f357cc838e5584">More...</a><br/></td></tr>
<tr class="separator:a8540999b4f1e41b762f357cc838e5584"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5a941faa36f4859e301a361c9001f99b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a5a941faa36f4859e301a361c9001f99b">XV_HDMIRX1_TMR2_STA_CNT_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a5a941faa36f4859e301a361c9001f99b"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Status counter Event mask.  <a href="#a5a941faa36f4859e301a361c9001f99b">More...</a><br/></td></tr>
<tr class="separator:a5a941faa36f4859e301a361c9001f99b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a262bcc996ce3a05ce2b5e69405164625"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a262bcc996ce3a05ce2b5e69405164625">XV_HDMIRX1_TMR3_STA_CNT_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:a262bcc996ce3a05ce2b5e69405164625"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Status counter Event mask.  <a href="#a262bcc996ce3a05ce2b5e69405164625">More...</a><br/></td></tr>
<tr class="separator:a262bcc996ce3a05ce2b5e69405164625"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2c6dbfd3edb699863544439e29145230"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a2c6dbfd3edb699863544439e29145230">XV_HDMIRX1_TMR4_STA_CNT_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:a2c6dbfd3edb699863544439e29145230"><td class="mdescLeft">&#160;</td><td class="mdescRight">TMR Status counter Event mask.  <a href="#a2c6dbfd3edb699863544439e29145230">More...</a><br/></td></tr>
<tr class="separator:a2c6dbfd3edb699863544439e29145230"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aef7c0f8c9f534cc7dbc8720d5a8911bb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aef7c0f8c9f534cc7dbc8720d5a8911bb">XV_HDMIRX1_VTD_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(0*4))</td></tr>
<tr class="memdesc:aef7c0f8c9f534cc7dbc8720d5a8911bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Identification Register offset.  <a href="#aef7c0f8c9f534cc7dbc8720d5a8911bb">More...</a><br/></td></tr>
<tr class="separator:aef7c0f8c9f534cc7dbc8720d5a8911bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a38f34bcb7e8f5d9de99c03aacd27353b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a38f34bcb7e8f5d9de99c03aacd27353b">XV_HDMIRX1_VTD_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(1*4))</td></tr>
<tr class="memdesc:a38f34bcb7e8f5d9de99c03aacd27353b"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control Register offset.  <a href="#a38f34bcb7e8f5d9de99c03aacd27353b">More...</a><br/></td></tr>
<tr class="separator:a38f34bcb7e8f5d9de99c03aacd27353b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a373df61175a1b81c8c49973a7c429c8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a373df61175a1b81c8c49973a7c429c8a">XV_HDMIRX1_VTD_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(2*4))</td></tr>
<tr class="memdesc:a373df61175a1b81c8c49973a7c429c8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control Set Register offset.  <a href="#a373df61175a1b81c8c49973a7c429c8a">More...</a><br/></td></tr>
<tr class="separator:a373df61175a1b81c8c49973a7c429c8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae971e94da9cfb5a7a9b682ae3526bb44"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae971e94da9cfb5a7a9b682ae3526bb44">XV_HDMIRX1_VTD_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(3*4))</td></tr>
<tr class="memdesc:ae971e94da9cfb5a7a9b682ae3526bb44"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control Clear Register offset.  <a href="#ae971e94da9cfb5a7a9b682ae3526bb44">More...</a><br/></td></tr>
<tr class="separator:ae971e94da9cfb5a7a9b682ae3526bb44"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7520909f353bdbc6da5cf59e436c0346"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7520909f353bdbc6da5cf59e436c0346">XV_HDMIRX1_VTD_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(4*4))</td></tr>
<tr class="memdesc:a7520909f353bdbc6da5cf59e436c0346"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status Register offset.  <a href="#a7520909f353bdbc6da5cf59e436c0346">More...</a><br/></td></tr>
<tr class="separator:a7520909f353bdbc6da5cf59e436c0346"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a31173bdc12d5d7c393e0ec4169a0e9bc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a31173bdc12d5d7c393e0ec4169a0e9bc">XV_HDMIRX1_VTD_TOT_PIX_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(5*4))</td></tr>
<tr class="memdesc:a31173bdc12d5d7c393e0ec4169a0e9bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Total Pixels Register offset.  <a href="#a31173bdc12d5d7c393e0ec4169a0e9bc">More...</a><br/></td></tr>
<tr class="separator:a31173bdc12d5d7c393e0ec4169a0e9bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaf231b8bf27d043648c5d4c18570e109"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aaf231b8bf27d043648c5d4c18570e109">XV_HDMIRX1_VTD_ACT_PIX_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(6*4))</td></tr>
<tr class="memdesc:aaf231b8bf27d043648c5d4c18570e109"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Active Pixels Register offset.  <a href="#aaf231b8bf27d043648c5d4c18570e109">More...</a><br/></td></tr>
<tr class="separator:aaf231b8bf27d043648c5d4c18570e109"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1130ed99163f49891fe76e84a2fd1ee0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1130ed99163f49891fe76e84a2fd1ee0">XV_HDMIRX1_VTD_TOT_LIN_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(7*4))</td></tr>
<tr class="memdesc:a1130ed99163f49891fe76e84a2fd1ee0"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Total Lines Register offset.  <a href="#a1130ed99163f49891fe76e84a2fd1ee0">More...</a><br/></td></tr>
<tr class="separator:a1130ed99163f49891fe76e84a2fd1ee0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae6e5fdc512cb7dc4f87aa5ddf8d87044"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae6e5fdc512cb7dc4f87aa5ddf8d87044">XV_HDMIRX1_VTD_ACT_LIN_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(8*4))</td></tr>
<tr class="memdesc:ae6e5fdc512cb7dc4f87aa5ddf8d87044"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Active Lines Register offset.  <a href="#ae6e5fdc512cb7dc4f87aa5ddf8d87044">More...</a><br/></td></tr>
<tr class="separator:ae6e5fdc512cb7dc4f87aa5ddf8d87044"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a881c6ffd3db18a7af39fe337d00eb179"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a881c6ffd3db18a7af39fe337d00eb179">XV_HDMIRX1_VTD_VSW_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(9*4))</td></tr>
<tr class="memdesc:a881c6ffd3db18a7af39fe337d00eb179"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Vertical Sync Width Register offset.  <a href="#a881c6ffd3db18a7af39fe337d00eb179">More...</a><br/></td></tr>
<tr class="separator:a881c6ffd3db18a7af39fe337d00eb179"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad49d4b9701fc528d4b35be9e0e0784b6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad49d4b9701fc528d4b35be9e0e0784b6">XV_HDMIRX1_VTD_HSW_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(10*4))</td></tr>
<tr class="memdesc:ad49d4b9701fc528d4b35be9e0e0784b6"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Horizontal Sync Width Register offset.  <a href="#ad49d4b9701fc528d4b35be9e0e0784b6">More...</a><br/></td></tr>
<tr class="separator:ad49d4b9701fc528d4b35be9e0e0784b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8b283a7d946febcf50815dc8ad31bf8d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a8b283a7d946febcf50815dc8ad31bf8d">XV_HDMIRX1_VTD_VFP_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(11*4))</td></tr>
<tr class="memdesc:a8b283a7d946febcf50815dc8ad31bf8d"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Vertical Front Porch Register offset.  <a href="#a8b283a7d946febcf50815dc8ad31bf8d">More...</a><br/></td></tr>
<tr class="separator:a8b283a7d946febcf50815dc8ad31bf8d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a655cb29d88325aab2476894e18a858fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a655cb29d88325aab2476894e18a858fe">XV_HDMIRX1_VTD_VBP_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(12*4))</td></tr>
<tr class="memdesc:a655cb29d88325aab2476894e18a858fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Vertical Back Porch Register offset.  <a href="#a655cb29d88325aab2476894e18a858fe">More...</a><br/></td></tr>
<tr class="separator:a655cb29d88325aab2476894e18a858fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aefb8dcc326ae1f421f1755d7eae42f2c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aefb8dcc326ae1f421f1755d7eae42f2c">XV_HDMIRX1_VTD_HFP_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(13*4))</td></tr>
<tr class="memdesc:aefb8dcc326ae1f421f1755d7eae42f2c"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Horizontal Front Porch Register offset.  <a href="#aefb8dcc326ae1f421f1755d7eae42f2c">More...</a><br/></td></tr>
<tr class="separator:aefb8dcc326ae1f421f1755d7eae42f2c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a29d81fca1318aa8e6dcb266ebf3eaf49"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a29d81fca1318aa8e6dcb266ebf3eaf49">XV_HDMIRX1_VTD_HBP_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(14*4))</td></tr>
<tr class="memdesc:a29d81fca1318aa8e6dcb266ebf3eaf49"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Horizontal Back Porch Register offset.  <a href="#a29d81fca1318aa8e6dcb266ebf3eaf49">More...</a><br/></td></tr>
<tr class="separator:a29d81fca1318aa8e6dcb266ebf3eaf49"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad3255aafdf1db8869d62b1ab51d58ad0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad3255aafdf1db8869d62b1ab51d58ad0">XV_HDMIRX1_VTD_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:ad3255aafdf1db8869d62b1ab51d58ad0"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control Run mask.  <a href="#ad3255aafdf1db8869d62b1ab51d58ad0">More...</a><br/></td></tr>
<tr class="separator:ad3255aafdf1db8869d62b1ab51d58ad0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a778b05c24de8ad264eb1fe2cc33e88af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a778b05c24de8ad264eb1fe2cc33e88af">XV_HDMIRX1_VTD_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a778b05c24de8ad264eb1fe2cc33e88af"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control Interrupt Enable mask.  <a href="#a778b05c24de8ad264eb1fe2cc33e88af">More...</a><br/></td></tr>
<tr class="separator:a778b05c24de8ad264eb1fe2cc33e88af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4e137d48421d51cab3ab2292ac749f0c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a4e137d48421d51cab3ab2292ac749f0c">XV_HDMIRX1_VTD_CTRL_FIELD_POL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a4e137d48421d51cab3ab2292ac749f0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control field polarity mask.  <a href="#a4e137d48421d51cab3ab2292ac749f0c">More...</a><br/></td></tr>
<tr class="separator:a4e137d48421d51cab3ab2292ac749f0c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a52153a206da2f6de52a47e4a96f70df9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a52153a206da2f6de52a47e4a96f70df9">XV_HDMIRX1_VTD_CTRL_SYNC_LOSS_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a52153a206da2f6de52a47e4a96f70df9"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control field polarity mask.  <a href="#a52153a206da2f6de52a47e4a96f70df9">More...</a><br/></td></tr>
<tr class="separator:a52153a206da2f6de52a47e4a96f70df9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0d60962ac4dd676e0835f784cb4fa8b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a0d60962ac4dd676e0835f784cb4fa8b3">XV_HDMIRX1_VTD_CTRL_VFP_ENABLE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:a0d60962ac4dd676e0835f784cb4fa8b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD VFP change interrupt enable mask.  <a href="#a0d60962ac4dd676e0835f784cb4fa8b3">More...</a><br/></td></tr>
<tr class="separator:a0d60962ac4dd676e0835f784cb4fa8b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aceaecabf406db886ed55dfe8f36abddc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aceaecabf406db886ed55dfe8f36abddc">XV_HDMIRX1_VTD_CTRL_TIMEBASE_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:aceaecabf406db886ed55dfe8f36abddc"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control timebase shift.  <a href="#aceaecabf406db886ed55dfe8f36abddc">More...</a><br/></td></tr>
<tr class="separator:aceaecabf406db886ed55dfe8f36abddc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac0f972a680a7e327fd805030bba7d7c6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac0f972a680a7e327fd805030bba7d7c6">XV_HDMIRX1_VTD_CTRL_TIMERBASE_MASK</a>&#160;&#160;&#160;0xffffff</td></tr>
<tr class="memdesc:ac0f972a680a7e327fd805030bba7d7c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Control timebase mask.  <a href="#ac0f972a680a7e327fd805030bba7d7c6">More...</a><br/></td></tr>
<tr class="separator:ac0f972a680a7e327fd805030bba7d7c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a979add2356c64b6b17d2e173b148a223"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a979add2356c64b6b17d2e173b148a223">XV_HDMIRX1_VTD_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a979add2356c64b6b17d2e173b148a223"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status Interrupt mask.  <a href="#a979add2356c64b6b17d2e173b148a223">More...</a><br/></td></tr>
<tr class="separator:a979add2356c64b6b17d2e173b148a223"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a580a0780c855eae7a5be6d14eaed70e0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a580a0780c855eae7a5be6d14eaed70e0">XV_HDMIRX1_VTD_STA_TIMEBASE_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a580a0780c855eae7a5be6d14eaed70e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status timebase event mask.  <a href="#a580a0780c855eae7a5be6d14eaed70e0">More...</a><br/></td></tr>
<tr class="separator:a580a0780c855eae7a5be6d14eaed70e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8451cdcae193a13f05a07d2b1d7c46f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a8451cdcae193a13f05a07d2b1d7c46f5">XV_HDMIRX1_VTD_STA_VS_POL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a8451cdcae193a13f05a07d2b1d7c46f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status Vsync Polarity mask.  <a href="#a8451cdcae193a13f05a07d2b1d7c46f5">More...</a><br/></td></tr>
<tr class="separator:a8451cdcae193a13f05a07d2b1d7c46f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac65a4d1a61da0cc29958b992c6096bc7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac65a4d1a61da0cc29958b992c6096bc7">XV_HDMIRX1_VTD_STA_HS_POL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:ac65a4d1a61da0cc29958b992c6096bc7"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status Hsync Polarity mask.  <a href="#ac65a4d1a61da0cc29958b992c6096bc7">More...</a><br/></td></tr>
<tr class="separator:ac65a4d1a61da0cc29958b992c6096bc7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1d7f91b7dd9418376b0f3b3ad33dffa9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1d7f91b7dd9418376b0f3b3ad33dffa9">XV_HDMIRX1_VTD_STA_FMT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:a1d7f91b7dd9418376b0f3b3ad33dffa9"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status Format mask.  <a href="#a1d7f91b7dd9418376b0f3b3ad33dffa9">More...</a><br/></td></tr>
<tr class="separator:a1d7f91b7dd9418376b0f3b3ad33dffa9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a36d63214bbba54dc596c75254384db59"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a36d63214bbba54dc596c75254384db59">XV_HDMIRX1_VTD_STA_SYNC_LOSS_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:a36d63214bbba54dc596c75254384db59"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status Sync Loss mask.  <a href="#a36d63214bbba54dc596c75254384db59">More...</a><br/></td></tr>
<tr class="separator:a36d63214bbba54dc596c75254384db59"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a95f2fd6152ac185b6fe4b47420610202"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a95f2fd6152ac185b6fe4b47420610202">XV_HDMIRX1_VTD_STA_VFP_CH_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:a95f2fd6152ac185b6fe4b47420610202"><td class="mdescLeft">&#160;</td><td class="mdescRight">VTD Status Vfp value chage mask.  <a href="#a95f2fd6152ac185b6fe4b47420610202">More...</a><br/></td></tr>
<tr class="separator:a95f2fd6152ac185b6fe4b47420610202"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f91dc6f41d5fa86e69fb60a99dffa12"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a3f91dc6f41d5fa86e69fb60a99dffa12">XV_HDMIRX1_DDC_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(0*4))</td></tr>
<tr class="memdesc:a3f91dc6f41d5fa86e69fb60a99dffa12"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Identification Register offset.  <a href="#a3f91dc6f41d5fa86e69fb60a99dffa12">More...</a><br/></td></tr>
<tr class="separator:a3f91dc6f41d5fa86e69fb60a99dffa12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7f2413f14093f11dd307db13281d253b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7f2413f14093f11dd307db13281d253b">XV_HDMIRX1_DDC_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(1*4))</td></tr>
<tr class="memdesc:a7f2413f14093f11dd307db13281d253b"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Register offset.  <a href="#a7f2413f14093f11dd307db13281d253b">More...</a><br/></td></tr>
<tr class="separator:a7f2413f14093f11dd307db13281d253b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a771754708a8fe2d29a65563db1a7a118"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a771754708a8fe2d29a65563db1a7a118">XV_HDMIRX1_DDC_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(2*4))</td></tr>
<tr class="memdesc:a771754708a8fe2d29a65563db1a7a118"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Register Set offset.  <a href="#a771754708a8fe2d29a65563db1a7a118">More...</a><br/></td></tr>
<tr class="separator:a771754708a8fe2d29a65563db1a7a118"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9cc9a4f86e3821f62a929d6d560a71d7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a9cc9a4f86e3821f62a929d6d560a71d7">XV_HDMIRX1_DDC_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(3*4))</td></tr>
<tr class="memdesc:a9cc9a4f86e3821f62a929d6d560a71d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Register Clear offset.  <a href="#a9cc9a4f86e3821f62a929d6d560a71d7">More...</a><br/></td></tr>
<tr class="separator:a9cc9a4f86e3821f62a929d6d560a71d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4b377386dc2f94f5fb4e17fb151245ab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a4b377386dc2f94f5fb4e17fb151245ab">XV_HDMIRX1_DDC_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(4*4))</td></tr>
<tr class="memdesc:a4b377386dc2f94f5fb4e17fb151245ab"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Register offset.  <a href="#a4b377386dc2f94f5fb4e17fb151245ab">More...</a><br/></td></tr>
<tr class="separator:a4b377386dc2f94f5fb4e17fb151245ab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abb393b7a8cc8cb837e91eb6b2f186ab0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#abb393b7a8cc8cb837e91eb6b2f186ab0">XV_HDMIRX1_DDC_EDID_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(5*4))</td></tr>
<tr class="memdesc:abb393b7a8cc8cb837e91eb6b2f186ab0"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC EDID Status Register offset.  <a href="#abb393b7a8cc8cb837e91eb6b2f186ab0">More...</a><br/></td></tr>
<tr class="separator:abb393b7a8cc8cb837e91eb6b2f186ab0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa2e6b62c7b7e30d408bd3743409310f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa2e6b62c7b7e30d408bd3743409310f9">XV_HDMIRX1_DDC_HDCP_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(6*4))</td></tr>
<tr class="memdesc:aa2e6b62c7b7e30d408bd3743409310f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC HDCP Status Register offset.  <a href="#aa2e6b62c7b7e30d408bd3743409310f9">More...</a><br/></td></tr>
<tr class="separator:aa2e6b62c7b7e30d408bd3743409310f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af89a39cd5eb513936da0abd0829cc94f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af89a39cd5eb513936da0abd0829cc94f">XV_HDMIRX1_DDC_EDID_SP_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(8*4))</td></tr>
<tr class="memdesc:af89a39cd5eb513936da0abd0829cc94f"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Read EDID segment pointer offset.  <a href="#af89a39cd5eb513936da0abd0829cc94f">More...</a><br/></td></tr>
<tr class="separator:af89a39cd5eb513936da0abd0829cc94f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a41c54aba350be9952f7b1b154234c1d6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a41c54aba350be9952f7b1b154234c1d6">XV_HDMIRX1_DDC_EDID_WP_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(9*4))</td></tr>
<tr class="memdesc:a41c54aba350be9952f7b1b154234c1d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Read EDID write pointer offset.  <a href="#a41c54aba350be9952f7b1b154234c1d6">More...</a><br/></td></tr>
<tr class="separator:a41c54aba350be9952f7b1b154234c1d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a184b9f548fd6200f08068baf652f324e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a184b9f548fd6200f08068baf652f324e">XV_HDMIRX1_DDC_EDID_RP_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(10*4))</td></tr>
<tr class="memdesc:a184b9f548fd6200f08068baf652f324e"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Read EDID read pointer offset.  <a href="#a184b9f548fd6200f08068baf652f324e">More...</a><br/></td></tr>
<tr class="separator:a184b9f548fd6200f08068baf652f324e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abcfd19bf175b5a1df19606aecdb38d54"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#abcfd19bf175b5a1df19606aecdb38d54">XV_HDMIRX1_DDC_EDID_DATA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(11*4))</td></tr>
<tr class="memdesc:abcfd19bf175b5a1df19606aecdb38d54"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Read EDID data offset.  <a href="#abcfd19bf175b5a1df19606aecdb38d54">More...</a><br/></td></tr>
<tr class="separator:abcfd19bf175b5a1df19606aecdb38d54"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8bbedc62df34078ef06647b7130e16f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a8bbedc62df34078ef06647b7130e16f4">XV_HDMIRX1_DDC_HDCP_ADDRESS_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(12*4))</td></tr>
<tr class="memdesc:a8bbedc62df34078ef06647b7130e16f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Read HDCP address offset.  <a href="#a8bbedc62df34078ef06647b7130e16f4">More...</a><br/></td></tr>
<tr class="separator:a8bbedc62df34078ef06647b7130e16f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ada994691776136b75789d9e343b4ce08"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ada994691776136b75789d9e343b4ce08">XV_HDMIRX1_DDC_HDCP_DATA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(13*4))</td></tr>
<tr class="memdesc:ada994691776136b75789d9e343b4ce08"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Read HDCP data offset.  <a href="#ada994691776136b75789d9e343b4ce08">More...</a><br/></td></tr>
<tr class="separator:ada994691776136b75789d9e343b4ce08"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad1701bdc9e14c9c171f210caee99219a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad1701bdc9e14c9c171f210caee99219a">XV_HDMIRX1_DDC_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:ad1701bdc9e14c9c171f210caee99219a"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Run mask.  <a href="#ad1701bdc9e14c9c171f210caee99219a">More...</a><br/></td></tr>
<tr class="separator:ad1701bdc9e14c9c171f210caee99219a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2e3e20ebe8b6d8378d84499355294b18"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a2e3e20ebe8b6d8378d84499355294b18">XV_HDMIRX1_DDC_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a2e3e20ebe8b6d8378d84499355294b18"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Interrupt enable mask.  <a href="#a2e3e20ebe8b6d8378d84499355294b18">More...</a><br/></td></tr>
<tr class="separator:a2e3e20ebe8b6d8378d84499355294b18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad4057a137cbf824dbce306e040b82c49"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad4057a137cbf824dbce306e040b82c49">XV_HDMIRX1_DDC_CTRL_EDID_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:ad4057a137cbf824dbce306e040b82c49"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control EDID enable mask.  <a href="#ad4057a137cbf824dbce306e040b82c49">More...</a><br/></td></tr>
<tr class="separator:ad4057a137cbf824dbce306e040b82c49"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af1c3bf86b1639762038aecd48e26e58e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af1c3bf86b1639762038aecd48e26e58e">XV_HDMIRX1_DDC_CTRL_SCDC_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:af1c3bf86b1639762038aecd48e26e58e"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control SCDC enable mask.  <a href="#af1c3bf86b1639762038aecd48e26e58e">More...</a><br/></td></tr>
<tr class="separator:af1c3bf86b1639762038aecd48e26e58e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3b8e0eb851af6c285e4d2a0c9a338604"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a3b8e0eb851af6c285e4d2a0c9a338604">XV_HDMIRX1_DDC_CTRL_HDCP_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:a3b8e0eb851af6c285e4d2a0c9a338604"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control HDCP enable mask.  <a href="#a3b8e0eb851af6c285e4d2a0c9a338604">More...</a><br/></td></tr>
<tr class="separator:a3b8e0eb851af6c285e4d2a0c9a338604"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad67f0253e5d43f97490f485ff58d7de4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad67f0253e5d43f97490f485ff58d7de4">XV_HDMIRX1_DDC_CTRL_SCDC_CLR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:ad67f0253e5d43f97490f485ff58d7de4"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control SCDC clear mask.  <a href="#ad67f0253e5d43f97490f485ff58d7de4">More...</a><br/></td></tr>
<tr class="separator:ad67f0253e5d43f97490f485ff58d7de4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adfbdf61fa82aba22cb7bb3240f6bdbfb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#adfbdf61fa82aba22cb7bb3240f6bdbfb">XV_HDMIRX1_DDC_CTRL_WMSG_CLR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:adfbdf61fa82aba22cb7bb3240f6bdbfb"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control write message clear mask.  <a href="#adfbdf61fa82aba22cb7bb3240f6bdbfb">More...</a><br/></td></tr>
<tr class="separator:adfbdf61fa82aba22cb7bb3240f6bdbfb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab3da38b5ded37f584afa3cdaa471ffc0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab3da38b5ded37f584afa3cdaa471ffc0">XV_HDMIRX1_DDC_CTRL_RMSG_CLR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:ab3da38b5ded37f584afa3cdaa471ffc0"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control read message clear mask.  <a href="#ab3da38b5ded37f584afa3cdaa471ffc0">More...</a><br/></td></tr>
<tr class="separator:ab3da38b5ded37f584afa3cdaa471ffc0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a49de50ec209773717034cf9cd694fdbb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a49de50ec209773717034cf9cd694fdbb">XV_HDMIRX1_DDC_CTRL_HDCP_MODE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:a49de50ec209773717034cf9cd694fdbb"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control HDCP mode mask.  <a href="#a49de50ec209773717034cf9cd694fdbb">More...</a><br/></td></tr>
<tr class="separator:a49de50ec209773717034cf9cd694fdbb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adcc224b817fe9b1fd2462875cf778dc6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#adcc224b817fe9b1fd2462875cf778dc6">XV_HDMIRX1_DDC_CTRL_SCDC_RD_WR_EVT_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;9)</td></tr>
<tr class="memdesc:adcc224b817fe9b1fd2462875cf778dc6"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control SCDC Read Write Event mask.  <a href="#adcc224b817fe9b1fd2462875cf778dc6">More...</a><br/></td></tr>
<tr class="separator:adcc224b817fe9b1fd2462875cf778dc6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1e194d82be050c88db0b276f30058fc1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1e194d82be050c88db0b276f30058fc1">XV_HDMIRX1_DDC_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a1e194d82be050c88db0b276f30058fc1"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Interrupt mask.  <a href="#a1e194d82be050c88db0b276f30058fc1">More...</a><br/></td></tr>
<tr class="separator:a1e194d82be050c88db0b276f30058fc1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3932971d83a493d116f0a8f63737f724"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a3932971d83a493d116f0a8f63737f724">XV_HDMIRX1_DDC_STA_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a3932971d83a493d116f0a8f63737f724"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Event mask.  <a href="#a3932971d83a493d116f0a8f63737f724">More...</a><br/></td></tr>
<tr class="separator:a3932971d83a493d116f0a8f63737f724"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0f3ee618abcb6825e8e7e9860155ffc3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a0f3ee618abcb6825e8e7e9860155ffc3">XV_HDMIRX1_DDC_STA_BUSY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a0f3ee618abcb6825e8e7e9860155ffc3"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Busy mask.  <a href="#a0f3ee618abcb6825e8e7e9860155ffc3">More...</a><br/></td></tr>
<tr class="separator:a0f3ee618abcb6825e8e7e9860155ffc3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aefcdacbbc2f6a3187ba765e7a4510c3a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aefcdacbbc2f6a3187ba765e7a4510c3a">XV_HDMIRX1_DDC_STA_SCL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:aefcdacbbc2f6a3187ba765e7a4510c3a"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status state of the SCL input mask.  <a href="#aefcdacbbc2f6a3187ba765e7a4510c3a">More...</a><br/></td></tr>
<tr class="separator:aefcdacbbc2f6a3187ba765e7a4510c3a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1df200f45cce4a44711143bb25b2514a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1df200f45cce4a44711143bb25b2514a">XV_HDMIRX1_DDC_STA_SDA_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:a1df200f45cce4a44711143bb25b2514a"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status state of the SDA input mask.  <a href="#a1df200f45cce4a44711143bb25b2514a">More...</a><br/></td></tr>
<tr class="separator:a1df200f45cce4a44711143bb25b2514a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa079a5050948a2f8d950e5e5dad4e83a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa079a5050948a2f8d950e5e5dad4e83a">XV_HDMIRX1_DDC_STA_HDCP_AKSV_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:aa079a5050948a2f8d950e5e5dad4e83a"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP AKSV event mask.  <a href="#aa079a5050948a2f8d950e5e5dad4e83a">More...</a><br/></td></tr>
<tr class="separator:aa079a5050948a2f8d950e5e5dad4e83a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ace0f3b7a95288004c3211af9fcbf078f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ace0f3b7a95288004c3211af9fcbf078f">XV_HDMIRX1_DDC_STA_HDCP_WMSG_NEW_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:ace0f3b7a95288004c3211af9fcbf078f"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP write message buffer new event mask.  <a href="#ace0f3b7a95288004c3211af9fcbf078f">More...</a><br/></td></tr>
<tr class="separator:ace0f3b7a95288004c3211af9fcbf078f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaf0a33f51c1375bfede67343049535a1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aaf0a33f51c1375bfede67343049535a1">XV_HDMIRX1_DDC_STA_HDCP_RMSG_END_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:aaf0a33f51c1375bfede67343049535a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP read message buffer end event mask.  <a href="#aaf0a33f51c1375bfede67343049535a1">More...</a><br/></td></tr>
<tr class="separator:aaf0a33f51c1375bfede67343049535a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adfb1be15f45bd1b408c5ac07ab37ed18"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#adfb1be15f45bd1b408c5ac07ab37ed18">XV_HDMIRX1_DDC_STA_HDCP_RMSG_NC_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:adfb1be15f45bd1b408c5ac07ab37ed18"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP read message buffer not completed event mask.  <a href="#adfb1be15f45bd1b408c5ac07ab37ed18">More...</a><br/></td></tr>
<tr class="separator:adfb1be15f45bd1b408c5ac07ab37ed18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abaf7f845011f382f1d52cc9e5596c33b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#abaf7f845011f382f1d52cc9e5596c33b">XV_HDMIRX1_DDC_STA_HDCP_1_PROT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;9)</td></tr>
<tr class="memdesc:abaf7f845011f382f1d52cc9e5596c33b"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 1.4 protocol flag.  <a href="#abaf7f845011f382f1d52cc9e5596c33b">More...</a><br/></td></tr>
<tr class="separator:abaf7f845011f382f1d52cc9e5596c33b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7df39564a89353925469e1e75868ffda"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7df39564a89353925469e1e75868ffda">XV_HDMIRX1_DDC_STA_HDCP_2_PROT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;10)</td></tr>
<tr class="memdesc:a7df39564a89353925469e1e75868ffda"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 protocol flag.  <a href="#a7df39564a89353925469e1e75868ffda">More...</a><br/></td></tr>
<tr class="separator:a7df39564a89353925469e1e75868ffda"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae2cef0c17f58092e296e1479464d1115"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae2cef0c17f58092e296e1479464d1115">XV_HDMIRX1_DDC_STA_HDCP_1_PROT_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;11)</td></tr>
<tr class="memdesc:ae2cef0c17f58092e296e1479464d1115"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 1.4 protocol event flag.  <a href="#ae2cef0c17f58092e296e1479464d1115">More...</a><br/></td></tr>
<tr class="separator:ae2cef0c17f58092e296e1479464d1115"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af0d3e6ec08e4edb7c641c6ddc513072d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af0d3e6ec08e4edb7c641c6ddc513072d">XV_HDMIRX1_DDC_STA_HDCP_2_PROT_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;12)</td></tr>
<tr class="memdesc:af0d3e6ec08e4edb7c641c6ddc513072d"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 protocol event flag.  <a href="#af0d3e6ec08e4edb7c641c6ddc513072d">More...</a><br/></td></tr>
<tr class="separator:af0d3e6ec08e4edb7c641c6ddc513072d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7922e751c958e0db943cfe707b7ca89b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7922e751c958e0db943cfe707b7ca89b">XV_HDMIRX1_DDC_STA_SCDC_RD_WR_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;13)</td></tr>
<tr class="memdesc:a7922e751c958e0db943cfe707b7ca89b"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status SCDC Read Write event flag.  <a href="#a7922e751c958e0db943cfe707b7ca89b">More...</a><br/></td></tr>
<tr class="separator:a7922e751c958e0db943cfe707b7ca89b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaa13fb19bafee84a5297a09ac97f6a4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aaa13fb19bafee84a5297a09ac97f6a4c">XV_HDMIRX1_DDC_STA_SCDC_DSC_STS_UPDT_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;14)</td></tr>
<tr class="memdesc:aaa13fb19bafee84a5297a09ac97f6a4c"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status 0x10 SCDC reg bit 0 Status_Update set by sink event flag.  <a href="#aaa13fb19bafee84a5297a09ac97f6a4c">More...</a><br/></td></tr>
<tr class="separator:aaa13fb19bafee84a5297a09ac97f6a4c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a885b5e8b024ee09446052c46f7e09bf8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a885b5e8b024ee09446052c46f7e09bf8">XV_HDMIRX1_DDC_STA_EDID_WORDS_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a885b5e8b024ee09446052c46f7e09bf8"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status EDID words shift.  <a href="#a885b5e8b024ee09446052c46f7e09bf8">More...</a><br/></td></tr>
<tr class="separator:a885b5e8b024ee09446052c46f7e09bf8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1696b82de3b20c5513c3ff4ee5015ba9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1696b82de3b20c5513c3ff4ee5015ba9">XV_HDMIRX1_DDC_STA_EDID_WORDS_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a1696b82de3b20c5513c3ff4ee5015ba9"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status EDID words mask.  <a href="#a1696b82de3b20c5513c3ff4ee5015ba9">More...</a><br/></td></tr>
<tr class="separator:a1696b82de3b20c5513c3ff4ee5015ba9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5adb107c4de97c736e7e7ab634212474"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a5adb107c4de97c736e7e7ab634212474">XV_HDMIRX1_DDC_STA_HDCP_WMSG_WORDS_MASK</a>&#160;&#160;&#160;0x7FF</td></tr>
<tr class="memdesc:a5adb107c4de97c736e7e7ab634212474"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 write message buffer words mask.  <a href="#a5adb107c4de97c736e7e7ab634212474">More...</a><br/></td></tr>
<tr class="separator:a5adb107c4de97c736e7e7ab634212474"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab61a6b938d6e9f9579506c97512c7729"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab61a6b938d6e9f9579506c97512c7729">XV_HDMIRX1_DDC_STA_HDCP_WMSG_WORDS_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ab61a6b938d6e9f9579506c97512c7729"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 write message buffer words shift.  <a href="#ab61a6b938d6e9f9579506c97512c7729">More...</a><br/></td></tr>
<tr class="separator:ab61a6b938d6e9f9579506c97512c7729"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa097132dd0838bf692d390fc1e28cbc9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa097132dd0838bf692d390fc1e28cbc9">XV_HDMIRX1_DDC_STA_HDCP_WMSG_EP_MASK</a>&#160;&#160;&#160;(1&lt;&lt;11)</td></tr>
<tr class="memdesc:aa097132dd0838bf692d390fc1e28cbc9"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 write message buffer empty mask.  <a href="#aa097132dd0838bf692d390fc1e28cbc9">More...</a><br/></td></tr>
<tr class="separator:aa097132dd0838bf692d390fc1e28cbc9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aee72508c9844747a42defa2b3f2ce8dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aee72508c9844747a42defa2b3f2ce8dc">XV_HDMIRX1_DDC_STA_HDCP_RMSG_WORDS_MASK</a>&#160;&#160;&#160;0x7FF</td></tr>
<tr class="memdesc:aee72508c9844747a42defa2b3f2ce8dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 read message buffer words mask.  <a href="#aee72508c9844747a42defa2b3f2ce8dc">More...</a><br/></td></tr>
<tr class="separator:aee72508c9844747a42defa2b3f2ce8dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a10fc375c829dc41f2417ba5f3ebc2fe5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a10fc375c829dc41f2417ba5f3ebc2fe5">XV_HDMIRX1_DDC_STA_HDCP_RMSG_WORDS_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a10fc375c829dc41f2417ba5f3ebc2fe5"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 read message buffer words shift.  <a href="#a10fc375c829dc41f2417ba5f3ebc2fe5">More...</a><br/></td></tr>
<tr class="separator:a10fc375c829dc41f2417ba5f3ebc2fe5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac65d331a8b1681442417b8a227c3e985"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac65d331a8b1681442417b8a227c3e985">XV_HDMIRX1_DDC_STA_HDCP_RMSG_EP_MASK</a>&#160;&#160;&#160;(1&lt;&lt;27)</td></tr>
<tr class="memdesc:ac65d331a8b1681442417b8a227c3e985"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status HDCP 2.2 read message buffer empty mask.  <a href="#ac65d331a8b1681442417b8a227c3e985">More...</a><br/></td></tr>
<tr class="separator:ac65d331a8b1681442417b8a227c3e985"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae8a61a7f2bdafdc54a96e2f2f923282e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae8a61a7f2bdafdc54a96e2f2f923282e">XV_HDMIRX1_AUX_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(0*4))</td></tr>
<tr class="memdesc:ae8a61a7f2bdafdc54a96e2f2f923282e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Identification Register offset.  <a href="#ae8a61a7f2bdafdc54a96e2f2f923282e">More...</a><br/></td></tr>
<tr class="separator:ae8a61a7f2bdafdc54a96e2f2f923282e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1c5746fc42b80fb22a390f6bb5d61d1b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1c5746fc42b80fb22a390f6bb5d61d1b">XV_HDMIRX1_AUX_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(1*4))</td></tr>
<tr class="memdesc:a1c5746fc42b80fb22a390f6bb5d61d1b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Register offset.  <a href="#a1c5746fc42b80fb22a390f6bb5d61d1b">More...</a><br/></td></tr>
<tr class="separator:a1c5746fc42b80fb22a390f6bb5d61d1b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac751b5b5be3fe003fe43f056f292bbf0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac751b5b5be3fe003fe43f056f292bbf0">XV_HDMIRX1_AUX_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(2*4))</td></tr>
<tr class="memdesc:ac751b5b5be3fe003fe43f056f292bbf0"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Register Set offset.  <a href="#ac751b5b5be3fe003fe43f056f292bbf0">More...</a><br/></td></tr>
<tr class="separator:ac751b5b5be3fe003fe43f056f292bbf0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:add9bba9228d3f408182b26777c21aa2b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#add9bba9228d3f408182b26777c21aa2b">XV_HDMIRX1_AUX_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(3*4))</td></tr>
<tr class="memdesc:add9bba9228d3f408182b26777c21aa2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Register Clear offset.  <a href="#add9bba9228d3f408182b26777c21aa2b">More...</a><br/></td></tr>
<tr class="separator:add9bba9228d3f408182b26777c21aa2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1ff1aa131b92f22cdadf41f72b41de10"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1ff1aa131b92f22cdadf41f72b41de10">XV_HDMIRX1_AUX_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(4*4))</td></tr>
<tr class="memdesc:a1ff1aa131b92f22cdadf41f72b41de10"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Register offset.  <a href="#a1ff1aa131b92f22cdadf41f72b41de10">More...</a><br/></td></tr>
<tr class="separator:a1ff1aa131b92f22cdadf41f72b41de10"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae86fb548d5cd48847264bd5b70b791b0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae86fb548d5cd48847264bd5b70b791b0">XV_HDMIRX1_AUX_DAT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(5*4))</td></tr>
<tr class="memdesc:ae86fb548d5cd48847264bd5b70b791b0"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Data Register offset.  <a href="#ae86fb548d5cd48847264bd5b70b791b0">More...</a><br/></td></tr>
<tr class="separator:ae86fb548d5cd48847264bd5b70b791b0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af2a5e3d2cee8f59c1fd5038fa30210e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af2a5e3d2cee8f59c1fd5038fa30210e6">XV_HDMIRX1_AUX_VTEM_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(7*4))</td></tr>
<tr class="memdesc:af2a5e3d2cee8f59c1fd5038fa30210e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX VTEM Register offset.  <a href="#af2a5e3d2cee8f59c1fd5038fa30210e6">More...</a><br/></td></tr>
<tr class="separator:af2a5e3d2cee8f59c1fd5038fa30210e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a12239713af1cb762261264aecd2db6db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a12239713af1cb762261264aecd2db6db">XV_HDMIRX1_AUX_FSYNC_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(8*4))</td></tr>
<tr class="memdesc:a12239713af1cb762261264aecd2db6db"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC Register offset.  <a href="#a12239713af1cb762261264aecd2db6db">More...</a><br/></td></tr>
<tr class="separator:a12239713af1cb762261264aecd2db6db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5153613accad3ead866f9eccd11c6065"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a5153613accad3ead866f9eccd11c6065">XV_HDMIRX1_AUX_FSYNC_PRO_OF</a>&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(9*4))</td></tr>
<tr class="memdesc:a5153613accad3ead866f9eccd11c6065"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FYNC PRO Register offset.  <a href="#a5153613accad3ead866f9eccd11c6065">More...</a><br/></td></tr>
<tr class="separator:a5153613accad3ead866f9eccd11c6065"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3ad16e42fdc47d009ff567cbf65d7ca0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a3ad16e42fdc47d009ff567cbf65d7ca0">XV_HDMIRX1_AUX_DYN_HDR_INFO_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE) + (10 * 4))</td></tr>
<tr class="memdesc:a3ad16e42fdc47d009ff567cbf65d7ca0"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Dynamic HDR Info offset.  <a href="#a3ad16e42fdc47d009ff567cbf65d7ca0">More...</a><br/></td></tr>
<tr class="separator:a3ad16e42fdc47d009ff567cbf65d7ca0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abd7ef1376fabe26cb32ece3c4efa7450"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#abd7ef1376fabe26cb32ece3c4efa7450">XV_HDMIRX1_AUX_DYN_HDR_STS_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE) + (11 * 4))</td></tr>
<tr class="memdesc:abd7ef1376fabe26cb32ece3c4efa7450"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Dynamic HDR Status offset.  <a href="#abd7ef1376fabe26cb32ece3c4efa7450">More...</a><br/></td></tr>
<tr class="separator:abd7ef1376fabe26cb32ece3c4efa7450"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab0a5740fe6d10b7c283a683e745518cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab0a5740fe6d10b7c283a683e745518cf">XV_HDMIRX1_AUX_DYN_HDR_MEMADDR_LSB_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE) + (12 * 4))</td></tr>
<tr class="memdesc:ab0a5740fe6d10b7c283a683e745518cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Lower address Dynamic HDR Status offset.  <a href="#ab0a5740fe6d10b7c283a683e745518cf">More...</a><br/></td></tr>
<tr class="separator:ab0a5740fe6d10b7c283a683e745518cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a94fec423e8bda97ee8cf9a7939e55aa5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a94fec423e8bda97ee8cf9a7939e55aa5">XV_HDMIRX1_AUX_DYN_HDR_MEMADDR_MSB_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE) + (13 * 4))</td></tr>
<tr class="memdesc:a94fec423e8bda97ee8cf9a7939e55aa5"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Higher address Dynamic HDR Status offset.  <a href="#a94fec423e8bda97ee8cf9a7939e55aa5">More...</a><br/></td></tr>
<tr class="separator:a94fec423e8bda97ee8cf9a7939e55aa5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac798bb32a30b17ca65d0f3371172963c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac798bb32a30b17ca65d0f3371172963c">XV_HDMIRX1_AUX_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:ac798bb32a30b17ca65d0f3371172963c"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Run mask.  <a href="#ac798bb32a30b17ca65d0f3371172963c">More...</a><br/></td></tr>
<tr class="separator:ac798bb32a30b17ca65d0f3371172963c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a983626c618f59a68cb6ef736c9f6d28a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a983626c618f59a68cb6ef736c9f6d28a">XV_HDMIRX1_AUX_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a983626c618f59a68cb6ef736c9f6d28a"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Interrupt Enable mask.  <a href="#a983626c618f59a68cb6ef736c9f6d28a">More...</a><br/></td></tr>
<tr class="separator:a983626c618f59a68cb6ef736c9f6d28a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0b6e46c9f463bf6c605f76ccc61c9f32"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a0b6e46c9f463bf6c605f76ccc61c9f32">XV_HDMIRX1_AUX_CTRL_FSYNC_VRR_CH_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a0b6e46c9f463bf6c605f76ccc61c9f32"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control FSync/VRR change event enable mask.  <a href="#a0b6e46c9f463bf6c605f76ccc61c9f32">More...</a><br/></td></tr>
<tr class="separator:a0b6e46c9f463bf6c605f76ccc61c9f32"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a63d7aee7a102a56cf637518d13307a12"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a63d7aee7a102a56cf637518d13307a12">XV_HDMIRX1_AUX_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a63d7aee7a102a56cf637518d13307a12"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Interrupt mask.  <a href="#a63d7aee7a102a56cf637518d13307a12">More...</a><br/></td></tr>
<tr class="separator:a63d7aee7a102a56cf637518d13307a12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8f725f6fec863ae9577ea9f2633d8672"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a8f725f6fec863ae9577ea9f2633d8672">XV_HDMIRX1_AUX_STA_NEW_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a8f725f6fec863ae9577ea9f2633d8672"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status New Packet mask.  <a href="#a8f725f6fec863ae9577ea9f2633d8672">More...</a><br/></td></tr>
<tr class="separator:a8f725f6fec863ae9577ea9f2633d8672"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae5429bc12ee91196b66bdad3d91bec53"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae5429bc12ee91196b66bdad3d91bec53">XV_HDMIRX1_AUX_STA_ERR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:ae5429bc12ee91196b66bdad3d91bec53"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status New Packet mask.  <a href="#ae5429bc12ee91196b66bdad3d91bec53">More...</a><br/></td></tr>
<tr class="separator:ae5429bc12ee91196b66bdad3d91bec53"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a22196adeeb4add191c26302017bfb8da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a22196adeeb4add191c26302017bfb8da">XV_HDMIRX1_AUX_STA_AVI_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a22196adeeb4add191c26302017bfb8da"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status AVI infoframe mask.  <a href="#a22196adeeb4add191c26302017bfb8da">More...</a><br/></td></tr>
<tr class="separator:a22196adeeb4add191c26302017bfb8da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad8888f01766a3c2663dbae99e1bbdf25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad8888f01766a3c2663dbae99e1bbdf25">XV_HDMIRX1_AUX_STA_GCP_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:ad8888f01766a3c2663dbae99e1bbdf25"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status General control packet mask.  <a href="#ad8888f01766a3c2663dbae99e1bbdf25">More...</a><br/></td></tr>
<tr class="separator:ad8888f01766a3c2663dbae99e1bbdf25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a711baf7875b3d07f131faebbce2bc7af"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a711baf7875b3d07f131faebbce2bc7af">XV_HDMIRX1_AUX_STA_FIFO_EP_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:a711baf7875b3d07f131faebbce2bc7af"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status FIFO Empty mask.  <a href="#a711baf7875b3d07f131faebbce2bc7af">More...</a><br/></td></tr>
<tr class="separator:a711baf7875b3d07f131faebbce2bc7af"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aae25cf4177044c69ea8981519b5ff454"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aae25cf4177044c69ea8981519b5ff454">XV_HDMIRX1_AUX_STA_FIFO_FL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:aae25cf4177044c69ea8981519b5ff454"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status FIFO Full mask.  <a href="#aae25cf4177044c69ea8981519b5ff454">More...</a><br/></td></tr>
<tr class="separator:aae25cf4177044c69ea8981519b5ff454"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a142f0f9898ec7f1fdfe87efbf3eeaf3f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a142f0f9898ec7f1fdfe87efbf3eeaf3f">XV_HDMIRX1_AUX_STA_DYN_HDR_EVT_MASK</a>&#160;&#160;&#160;(1 &lt;&lt; 20)</td></tr>
<tr class="memdesc:a142f0f9898ec7f1fdfe87efbf3eeaf3f"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Dynamic HDR packet received event mask.  <a href="#a142f0f9898ec7f1fdfe87efbf3eeaf3f">More...</a><br/></td></tr>
<tr class="separator:a142f0f9898ec7f1fdfe87efbf3eeaf3f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2e3307e88b0574b011aeb988375a091e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a2e3307e88b0574b011aeb988375a091e">XV_HDMIRX1_AUX_STA_VRR_CD_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;21)</td></tr>
<tr class="memdesc:a2e3307e88b0574b011aeb988375a091e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status VRR CD mask.  <a href="#a2e3307e88b0574b011aeb988375a091e">More...</a><br/></td></tr>
<tr class="separator:a2e3307e88b0574b011aeb988375a091e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aef8262d6088e54669226459118cdae1f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aef8262d6088e54669226459118cdae1f">XV_HDMIRX1_AUX_STA_FSYNC_CD_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;22)</td></tr>
<tr class="memdesc:aef8262d6088e54669226459118cdae1f"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status FSYNC CD mask.  <a href="#aef8262d6088e54669226459118cdae1f">More...</a><br/></td></tr>
<tr class="separator:aef8262d6088e54669226459118cdae1f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6e4260d14636c843678d98e6c6cb6648"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a6e4260d14636c843678d98e6c6cb6648">XV_HDMIRX1_AUX_STA_GCP_CD_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;25)</td></tr>
<tr class="memdesc:a6e4260d14636c843678d98e6c6cb6648"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status GCP ColorDepth mask.  <a href="#a6e4260d14636c843678d98e6c6cb6648">More...</a><br/></td></tr>
<tr class="separator:a6e4260d14636c843678d98e6c6cb6648"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adb74b7eab29b6ddea685e95b17e85cbd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#adb74b7eab29b6ddea685e95b17e85cbd">XV_HDMIRX1_AUX_STA_GCP_AVMUTE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;31)</td></tr>
<tr class="memdesc:adb74b7eab29b6ddea685e95b17e85cbd"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status GCP avmute mask.  <a href="#adb74b7eab29b6ddea685e95b17e85cbd">More...</a><br/></td></tr>
<tr class="separator:adb74b7eab29b6ddea685e95b17e85cbd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7ab9bb403ffe88b36b5ad9f8dc1b28aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7ab9bb403ffe88b36b5ad9f8dc1b28aa">XV_HDMIRX1_AUX_STA_AVI_VIC_MASK</a>&#160;&#160;&#160;0xFF</td></tr>
<tr class="memdesc:a7ab9bb403ffe88b36b5ad9f8dc1b28aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status AVI VIC mask.  <a href="#a7ab9bb403ffe88b36b5ad9f8dc1b28aa">More...</a><br/></td></tr>
<tr class="separator:a7ab9bb403ffe88b36b5ad9f8dc1b28aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae4df89df74ea61966284a00390fc2754"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae4df89df74ea61966284a00390fc2754">XV_HDMIRX1_AUX_STA_AVI_CS_MASK</a>&#160;&#160;&#160;0x03</td></tr>
<tr class="memdesc:ae4df89df74ea61966284a00390fc2754"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status AVI colorspace mask.  <a href="#ae4df89df74ea61966284a00390fc2754">More...</a><br/></td></tr>
<tr class="separator:ae4df89df74ea61966284a00390fc2754"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a42156911fe2a4d3c5ac885ab25f63008"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a42156911fe2a4d3c5ac885ab25f63008">XV_HDMIRX1_AUX_STA_GCP_CD_MASK</a>&#160;&#160;&#160;0x03</td></tr>
<tr class="memdesc:a42156911fe2a4d3c5ac885ab25f63008"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status GCP colordepth mask.  <a href="#a42156911fe2a4d3c5ac885ab25f63008">More...</a><br/></td></tr>
<tr class="separator:a42156911fe2a4d3c5ac885ab25f63008"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae0dca7c1eb9891f5021107ba4f8600e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae0dca7c1eb9891f5021107ba4f8600e3">XV_HDMIRX1_AUX_STA_GCP_PP_MASK</a>&#160;&#160;&#160;0x07</td></tr>
<tr class="memdesc:ae0dca7c1eb9891f5021107ba4f8600e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status GCP pixel phase mask.  <a href="#ae0dca7c1eb9891f5021107ba4f8600e3">More...</a><br/></td></tr>
<tr class="separator:ae0dca7c1eb9891f5021107ba4f8600e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abffc2c8a5b1e99d2698108754af68ee2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#abffc2c8a5b1e99d2698108754af68ee2">XV_HDMIRX1_AUX_STA_AVI_VIC_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:abffc2c8a5b1e99d2698108754af68ee2"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status AVI VIC Shift.  <a href="#abffc2c8a5b1e99d2698108754af68ee2">More...</a><br/></td></tr>
<tr class="separator:abffc2c8a5b1e99d2698108754af68ee2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ade847b0f35ba1afad9843e799adb7bbe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ade847b0f35ba1afad9843e799adb7bbe">XV_HDMIRX1_AUX_STA_AVI_CS_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ade847b0f35ba1afad9843e799adb7bbe"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status AVI colorspace Shift.  <a href="#ade847b0f35ba1afad9843e799adb7bbe">More...</a><br/></td></tr>
<tr class="separator:ade847b0f35ba1afad9843e799adb7bbe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a27b0a9a2dc2e2d4e567e6f2a9d5413d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a27b0a9a2dc2e2d4e567e6f2a9d5413d3">XV_HDMIRX1_AUX_STA_FSYNC_RDY_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:a27b0a9a2dc2e2d4e567e6f2a9d5413d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status FSYNC RDY shift.  <a href="#a27b0a9a2dc2e2d4e567e6f2a9d5413d3">More...</a><br/></td></tr>
<tr class="separator:a27b0a9a2dc2e2d4e567e6f2a9d5413d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a678dd837feda71420c60dc2588a46db3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a678dd837feda71420c60dc2588a46db3">XV_HDMIRX1_AUX_STA_VRR_RDY_SHIFT</a>&#160;&#160;&#160;23</td></tr>
<tr class="memdesc:a678dd837feda71420c60dc2588a46db3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status VRR RDY shift.  <a href="#a678dd837feda71420c60dc2588a46db3">More...</a><br/></td></tr>
<tr class="separator:a678dd837feda71420c60dc2588a46db3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa32fc692224b983ed8c19d6667bcb3d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa32fc692224b983ed8c19d6667bcb3d8">XV_HDMIRX1_AUX_STA_GCP_CD_SHIFT</a>&#160;&#160;&#160;26</td></tr>
<tr class="memdesc:aa32fc692224b983ed8c19d6667bcb3d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status GCP colordepth Shift.  <a href="#aa32fc692224b983ed8c19d6667bcb3d8">More...</a><br/></td></tr>
<tr class="separator:aa32fc692224b983ed8c19d6667bcb3d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa0c7dd62a11c1e1bb3991484530abac5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa0c7dd62a11c1e1bb3991484530abac5">XV_HDMIRX1_AUX_STA_GCP_PP_SHIFT</a>&#160;&#160;&#160;28</td></tr>
<tr class="memdesc:aa0c7dd62a11c1e1bb3991484530abac5"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status GCP pixel phase Shift.  <a href="#aa0c7dd62a11c1e1bb3991484530abac5">More...</a><br/></td></tr>
<tr class="separator:aa0c7dd62a11c1e1bb3991484530abac5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f8869ac167a6200811478930459c1d7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a3f8869ac167a6200811478930459c1d7">XV_HDMIRX1_AUX_VTEM_VRR_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a3f8869ac167a6200811478930459c1d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX VTEM VRR Enable mask.  <a href="#a3f8869ac167a6200811478930459c1d7">More...</a><br/></td></tr>
<tr class="separator:a3f8869ac167a6200811478930459c1d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac485a09c3c426c340310b6203177840b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac485a09c3c426c340310b6203177840b">XV_HDMIRX1_AUX_VTEM_M_CONST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:ac485a09c3c426c340310b6203177840b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX VTEM M_CONST mask.  <a href="#ac485a09c3c426c340310b6203177840b">More...</a><br/></td></tr>
<tr class="separator:ac485a09c3c426c340310b6203177840b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae32c85b9d53de97722713750479ce5f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae32c85b9d53de97722713750479ce5f4">XV_HDMIRX1_AUX_VTEM_FVA_FACT_M1_MASK</a>&#160;&#160;&#160;((0xF) &lt;&lt; 2)</td></tr>
<tr class="memdesc:ae32c85b9d53de97722713750479ce5f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX VTEM FVA Factor minus 1 mask.  <a href="#ae32c85b9d53de97722713750479ce5f4">More...</a><br/></td></tr>
<tr class="separator:ae32c85b9d53de97722713750479ce5f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a4ed1a0301fd76c707434392a8267f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1a4ed1a0301fd76c707434392a8267f3">XV_HDMIRX1_AUX_VTEM_RB_MASK</a>&#160;&#160;&#160;(1&lt;&lt;26)</td></tr>
<tr class="memdesc:a1a4ed1a0301fd76c707434392a8267f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX VTEM Reduced blanking mask.  <a href="#a1a4ed1a0301fd76c707434392a8267f3">More...</a><br/></td></tr>
<tr class="separator:a1a4ed1a0301fd76c707434392a8267f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a55d917991044df301851eeeb3623e88d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a55d917991044df301851eeeb3623e88d">XV_HDMIRX1_AUX_VTEM_BASE_VFRONT_MASK</a>&#160;&#160;&#160;((0xFF) &lt;&lt; 8)</td></tr>
<tr class="memdesc:a55d917991044df301851eeeb3623e88d"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX VTEM Reduced blanking mask.  <a href="#a55d917991044df301851eeeb3623e88d">More...</a><br/></td></tr>
<tr class="separator:a55d917991044df301851eeeb3623e88d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8a951608e8917bc25eb1f8a339650967"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a8a951608e8917bc25eb1f8a339650967">XV_HDMIRX1_AUX_VTEM_BASE_REFRESH_RATE_MASK</a>&#160;&#160;&#160;((0x3FF) &lt;&lt; 16)</td></tr>
<tr class="memdesc:a8a951608e8917bc25eb1f8a339650967"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX VTEM Base refresh rate mask.  <a href="#a8a951608e8917bc25eb1f8a339650967">More...</a><br/></td></tr>
<tr class="separator:a8a951608e8917bc25eb1f8a339650967"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7378ef7ea017959041c7e4950126866b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7378ef7ea017959041c7e4950126866b">XV_HDMIRX1_AUX_VTEM_QMS_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:a7378ef7ea017959041c7e4950126866b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX VTEM QMS Enable mask.  <a href="#a7378ef7ea017959041c7e4950126866b">More...</a><br/></td></tr>
<tr class="separator:a7378ef7ea017959041c7e4950126866b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7093a8c20be4f88fbd0fa90af073c813"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7093a8c20be4f88fbd0fa90af073c813">XV_HDMIRX1_AUX_VTEM_NEXT_TFR_MASK</a>&#160;&#160;&#160;((0x1F) &lt;&lt; 27)</td></tr>
<tr class="memdesc:a7093a8c20be4f88fbd0fa90af073c813"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX VTEM Next transfer rate mask.  <a href="#a7093a8c20be4f88fbd0fa90af073c813">More...</a><br/></td></tr>
<tr class="separator:a7093a8c20be4f88fbd0fa90af073c813"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a47d74d4099c3762aec278c25dce3dfbf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a47d74d4099c3762aec278c25dce3dfbf">XV_HDMIRX1_AUX_FSYNC_VERSION_MASK</a>&#160;&#160;&#160;0xFF</td></tr>
<tr class="memdesc:a47d74d4099c3762aec278c25dce3dfbf"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC Version mask.  <a href="#a47d74d4099c3762aec278c25dce3dfbf">More...</a><br/></td></tr>
<tr class="separator:a47d74d4099c3762aec278c25dce3dfbf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4fb3f6534cc5c73d820e52d2c47a20d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a4fb3f6534cc5c73d820e52d2c47a20d2">XV_HDMIRX1_AUX_FSYNC_SUPPORT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:a4fb3f6534cc5c73d820e52d2c47a20d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC Support mask.  <a href="#a4fb3f6534cc5c73d820e52d2c47a20d2">More...</a><br/></td></tr>
<tr class="separator:a4fb3f6534cc5c73d820e52d2c47a20d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab1cc8a2ea931e8964a9da817be414b53"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab1cc8a2ea931e8964a9da817be414b53">XV_HDMIRX1_AUX_FSYNC_ENABLED_MASK</a>&#160;&#160;&#160;(1&lt;&lt;9)</td></tr>
<tr class="memdesc:ab1cc8a2ea931e8964a9da817be414b53"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC Enabled mask.  <a href="#ab1cc8a2ea931e8964a9da817be414b53">More...</a><br/></td></tr>
<tr class="separator:ab1cc8a2ea931e8964a9da817be414b53"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a459e57839a799f6d970783e7e380a16f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a459e57839a799f6d970783e7e380a16f">XV_HDMIRX1_AUX_FSYNC_ACTIVE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;10)</td></tr>
<tr class="memdesc:a459e57839a799f6d970783e7e380a16f"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC Active mask.  <a href="#a459e57839a799f6d970783e7e380a16f">More...</a><br/></td></tr>
<tr class="separator:a459e57839a799f6d970783e7e380a16f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a83319e61d134f2b82dc3160ad445b3b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a83319e61d134f2b82dc3160ad445b3b7">XV_HDMIRX1_AUX_FSYNC_PRO_NTV_CS_ACT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;11)</td></tr>
<tr class="memdesc:a83319e61d134f2b82dc3160ad445b3b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC Pro Native Color space active mask.  <a href="#a83319e61d134f2b82dc3160ad445b3b7">More...</a><br/></td></tr>
<tr class="separator:a83319e61d134f2b82dc3160ad445b3b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a96cb820fa92f0e5ce5ed55d757683f74"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a96cb820fa92f0e5ce5ed55d757683f74">XV_HDMIRX1_AUX_FSYNC_PRO_BRIGHT_CTRL_ACT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;12)</td></tr>
<tr class="memdesc:a96cb820fa92f0e5ce5ed55d757683f74"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC Pro Brightness Control Active mask.  <a href="#a96cb820fa92f0e5ce5ed55d757683f74">More...</a><br/></td></tr>
<tr class="separator:a96cb820fa92f0e5ce5ed55d757683f74"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a28d8d143ae40f61877646b8b76c82c67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a28d8d143ae40f61877646b8b76c82c67">XV_HDMIRX1_AUX_FSYNC_PRO_LDIMM_CTRL_ACT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;13)</td></tr>
<tr class="memdesc:a28d8d143ae40f61877646b8b76c82c67"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC Pro Seamless Local Dimming Disable Control mask.  <a href="#a28d8d143ae40f61877646b8b76c82c67">More...</a><br/></td></tr>
<tr class="separator:a28d8d143ae40f61877646b8b76c82c67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9aca9ff422ac8a1889a2f61f7ff5e016"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a9aca9ff422ac8a1889a2f61f7ff5e016">XV_HDMIRX1_AUX_FSYNC_MIN_REF_RATE_MASK</a>&#160;&#160;&#160;(0xFF &lt;&lt; 16)</td></tr>
<tr class="memdesc:a9aca9ff422ac8a1889a2f61f7ff5e016"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC FreeSync Minimum refresh rate mask.  <a href="#a9aca9ff422ac8a1889a2f61f7ff5e016">More...</a><br/></td></tr>
<tr class="separator:a9aca9ff422ac8a1889a2f61f7ff5e016"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6a9349c7dacd7f66810c4d23192e0b15"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a6a9349c7dacd7f66810c4d23192e0b15">XV_HDMIRX1_AUX_FSYNC_MAX_REF_RATE_MASK</a>&#160;&#160;&#160;(0xFF &lt;&lt; 24)</td></tr>
<tr class="memdesc:a6a9349c7dacd7f66810c4d23192e0b15"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC FreeSync Maximum refresh rate mask.  <a href="#a6a9349c7dacd7f66810c4d23192e0b15">More...</a><br/></td></tr>
<tr class="separator:a6a9349c7dacd7f66810c4d23192e0b15"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acd3572d489259202bce0a73190ace2f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#acd3572d489259202bce0a73190ace2f7">XV_HDMIRX1_AUX_FSYNC_PRO_SRGB_EOTF_MASK</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:acd3572d489259202bce0a73190ace2f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC SRGB_EOTF mask.  <a href="#acd3572d489259202bce0a73190ace2f7">More...</a><br/></td></tr>
<tr class="separator:acd3572d489259202bce0a73190ace2f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8f6ebecc8a9e684942972cd5f4479996"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a8f6ebecc8a9e684942972cd5f4479996">XV_HDMIRX1_AUX_FSYNC_PRO_BT709_EOTF_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a8f6ebecc8a9e684942972cd5f4479996"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC BT709_EOTF mask.  <a href="#a8f6ebecc8a9e684942972cd5f4479996">More...</a><br/></td></tr>
<tr class="separator:a8f6ebecc8a9e684942972cd5f4479996"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aadbf74d597b66d123380cd6e28848933"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aadbf74d597b66d123380cd6e28848933">XV_HDMIRX1_AUX_FSYNC_PRO_GAMMA_2_2_EOTF_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:aadbf74d597b66d123380cd6e28848933"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC GAMMA_2_2_EOTF mask.  <a href="#aadbf74d597b66d123380cd6e28848933">More...</a><br/></td></tr>
<tr class="separator:aadbf74d597b66d123380cd6e28848933"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af9c4b47bff7449a82fc8b1c1b099034f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af9c4b47bff7449a82fc8b1c1b099034f">XV_HDMIRX1_AUX_FSYNC_PRO_GAMMA_2_6_EOTF_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:af9c4b47bff7449a82fc8b1c1b099034f"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC GAMMA_2_6_EOTF mask.  <a href="#af9c4b47bff7449a82fc8b1c1b099034f">More...</a><br/></td></tr>
<tr class="separator:af9c4b47bff7449a82fc8b1c1b099034f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a7fabb9ff27d7b01f04e175c32efb89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1a7fabb9ff27d7b01f04e175c32efb89">XV_HDMIRX1_AUX_FSYNC_PRO_PQ_EOTF_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:a1a7fabb9ff27d7b01f04e175c32efb89"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC PQ_EOTF mask.  <a href="#a1a7fabb9ff27d7b01f04e175c32efb89">More...</a><br/></td></tr>
<tr class="separator:a1a7fabb9ff27d7b01f04e175c32efb89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aef890fc9e3d1905a5c18c96dcbc0b7f1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aef890fc9e3d1905a5c18c96dcbc0b7f1">XV_HDMIRX1_AUX_FSYNC_PRO_BRIGHT_CTRL_MASK</a>&#160;&#160;&#160;(0xFF &lt;&lt; 16)</td></tr>
<tr class="memdesc:aef890fc9e3d1905a5c18c96dcbc0b7f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX FSYNC BRIGHT_CTRL mask.  <a href="#aef890fc9e3d1905a5c18c96dcbc0b7f1">More...</a><br/></td></tr>
<tr class="separator:aef890fc9e3d1905a5c18c96dcbc0b7f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a52d316fb63d45bfdcd8def3b5503ef03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a52d316fb63d45bfdcd8def3b5503ef03">XV_HDMIRX1_AUX_DYN_HDR_STS_GOF_MASK</a>&#160;&#160;&#160;(1)</td></tr>
<tr class="memdesc:a52d316fb63d45bfdcd8def3b5503ef03"><td class="mdescLeft">&#160;</td><td class="mdescRight">Graphics Overlay Flag.  <a href="#a52d316fb63d45bfdcd8def3b5503ef03">More...</a><br/></td></tr>
<tr class="separator:a52d316fb63d45bfdcd8def3b5503ef03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:add06acac6296880fa714d3265160890d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#add06acac6296880fa714d3265160890d">XV_HDMIRX1_AUX_DYN_HDR_STS_ERR_MASK</a>&#160;&#160;&#160;(0x3 &lt;&lt; 1)</td></tr>
<tr class="memdesc:add06acac6296880fa714d3265160890d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Errors asserted while writing ot memory.  <a href="#add06acac6296880fa714d3265160890d">More...</a><br/></td></tr>
<tr class="separator:add06acac6296880fa714d3265160890d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae9b202d8c94989184154789ae50cf7e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae9b202d8c94989184154789ae50cf7e4">XV_HDMIRX1_AUD_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUD_BASE)+(0*4))</td></tr>
<tr class="memdesc:ae9b202d8c94989184154789ae50cf7e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Identification Register offset.  <a href="#ae9b202d8c94989184154789ae50cf7e4">More...</a><br/></td></tr>
<tr class="separator:ae9b202d8c94989184154789ae50cf7e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a10826337df9a2f1577909678bfeea831"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a10826337df9a2f1577909678bfeea831">XV_HDMIRX1_AUD_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUD_BASE)+(1*4))</td></tr>
<tr class="memdesc:a10826337df9a2f1577909678bfeea831"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Register offset.  <a href="#a10826337df9a2f1577909678bfeea831">More...</a><br/></td></tr>
<tr class="separator:a10826337df9a2f1577909678bfeea831"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6144291d33bdfd02d9077042fb6a5f0d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a6144291d33bdfd02d9077042fb6a5f0d">XV_HDMIRX1_AUD_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUD_BASE)+(2*4))</td></tr>
<tr class="memdesc:a6144291d33bdfd02d9077042fb6a5f0d"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Register Set offset.  <a href="#a6144291d33bdfd02d9077042fb6a5f0d">More...</a><br/></td></tr>
<tr class="separator:a6144291d33bdfd02d9077042fb6a5f0d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac3b08fa2ae41be9a6904419b439d79f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac3b08fa2ae41be9a6904419b439d79f3">XV_HDMIRX1_AUD_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUD_BASE)+(3*4))</td></tr>
<tr class="memdesc:ac3b08fa2ae41be9a6904419b439d79f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Register Clear offset.  <a href="#ac3b08fa2ae41be9a6904419b439d79f3">More...</a><br/></td></tr>
<tr class="separator:ac3b08fa2ae41be9a6904419b439d79f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6b471c291404420baf14808dc39da8e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a6b471c291404420baf14808dc39da8e4">XV_HDMIRX1_AUD_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUD_BASE)+(4*4))</td></tr>
<tr class="memdesc:a6b471c291404420baf14808dc39da8e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Register offset.  <a href="#a6b471c291404420baf14808dc39da8e4">More...</a><br/></td></tr>
<tr class="separator:a6b471c291404420baf14808dc39da8e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a29e933929edb889a5cf22e2b358bcbd6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a29e933929edb889a5cf22e2b358bcbd6">XV_HDMIRX1_AUD_CTS_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUD_BASE)+(5*4))</td></tr>
<tr class="memdesc:a29e933929edb889a5cf22e2b358bcbd6"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD CTS Register offset.  <a href="#a29e933929edb889a5cf22e2b358bcbd6">More...</a><br/></td></tr>
<tr class="separator:a29e933929edb889a5cf22e2b358bcbd6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa108342fb6a7cb47e297368082ba4943"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa108342fb6a7cb47e297368082ba4943">XV_HDMIRX1_AUD_N_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_AUD_BASE)+(6*4))</td></tr>
<tr class="memdesc:aa108342fb6a7cb47e297368082ba4943"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD N Register offset.  <a href="#aa108342fb6a7cb47e297368082ba4943">More...</a><br/></td></tr>
<tr class="separator:aa108342fb6a7cb47e297368082ba4943"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a025c0ac63f58c4d1b532ce2c49cc168d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a025c0ac63f58c4d1b532ce2c49cc168d">XV_HDMIRX1_AUD_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a025c0ac63f58c4d1b532ce2c49cc168d"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Run mask.  <a href="#a025c0ac63f58c4d1b532ce2c49cc168d">More...</a><br/></td></tr>
<tr class="separator:a025c0ac63f58c4d1b532ce2c49cc168d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad9cead30e8cec1e057a5670382f85aac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad9cead30e8cec1e057a5670382f85aac">XV_HDMIRX1_AUD_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:ad9cead30e8cec1e057a5670382f85aac"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Interrupt Enable mask.  <a href="#ad9cead30e8cec1e057a5670382f85aac">More...</a><br/></td></tr>
<tr class="separator:ad9cead30e8cec1e057a5670382f85aac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acebfc50acd8328e43d89fd4d297eb9b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#acebfc50acd8328e43d89fd4d297eb9b7">XV_HDMIRX1_AUD_CTRL_ACR_UPD_EVT_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:acebfc50acd8328e43d89fd4d297eb9b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control ACR Update Event Enable mask.  <a href="#acebfc50acd8328e43d89fd4d297eb9b7">More...</a><br/></td></tr>
<tr class="separator:acebfc50acd8328e43d89fd4d297eb9b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9b671fa1d778ce26fb96731f95660999"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a9b671fa1d778ce26fb96731f95660999">XV_HDMIRX1_AUD_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a9b671fa1d778ce26fb96731f95660999"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Interrupt mask.  <a href="#a9b671fa1d778ce26fb96731f95660999">More...</a><br/></td></tr>
<tr class="separator:a9b671fa1d778ce26fb96731f95660999"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0764f4406426ea7680979d7cf13f5409"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a0764f4406426ea7680979d7cf13f5409">XV_HDMIRX1_AUD_STA_ACT_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a0764f4406426ea7680979d7cf13f5409"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Event mask.  <a href="#a0764f4406426ea7680979d7cf13f5409">More...</a><br/></td></tr>
<tr class="separator:a0764f4406426ea7680979d7cf13f5409"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2af8b2bd0e80317e44eec5d45891d52b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a2af8b2bd0e80317e44eec5d45891d52b">XV_HDMIRX1_AUD_STA_CH_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a2af8b2bd0e80317e44eec5d45891d52b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Event mask.  <a href="#a2af8b2bd0e80317e44eec5d45891d52b">More...</a><br/></td></tr>
<tr class="separator:a2af8b2bd0e80317e44eec5d45891d52b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1379c3a28e0344be55fa32908b17626e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1379c3a28e0344be55fa32908b17626e">XV_HDMIRX1_AUD_STA_ACT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a1379c3a28e0344be55fa32908b17626e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Active mask.  <a href="#a1379c3a28e0344be55fa32908b17626e">More...</a><br/></td></tr>
<tr class="separator:a1379c3a28e0344be55fa32908b17626e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af462fd88e1f6c3e1e0015534b78014ee"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af462fd88e1f6c3e1e0015534b78014ee">XV_HDMIRX1_AUD_STA_AUD_CH_MASK</a>&#160;&#160;&#160;0x03</td></tr>
<tr class="memdesc:af462fd88e1f6c3e1e0015534b78014ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Audio channel mask.  <a href="#af462fd88e1f6c3e1e0015534b78014ee">More...</a><br/></td></tr>
<tr class="separator:af462fd88e1f6c3e1e0015534b78014ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a89a6281a9f59ff584150a1b43f0c2fec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a89a6281a9f59ff584150a1b43f0c2fec">XV_HDMIRX1_AUD_STA_AUD_CH_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:a89a6281a9f59ff584150a1b43f0c2fec"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Audio channel Shift.  <a href="#a89a6281a9f59ff584150a1b43f0c2fec">More...</a><br/></td></tr>
<tr class="separator:a89a6281a9f59ff584150a1b43f0c2fec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a43a10555bb908231f981067b8551250f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a43a10555bb908231f981067b8551250f">XV_HDMIRX1_AUD_STA_3DAUD_CH_MASK</a>&#160;&#160;&#160;0x07</td></tr>
<tr class="memdesc:a43a10555bb908231f981067b8551250f"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Audio channel mask.  <a href="#a43a10555bb908231f981067b8551250f">More...</a><br/></td></tr>
<tr class="separator:a43a10555bb908231f981067b8551250f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af5e43e9852b0db94bde0c0c7dfdea59c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af5e43e9852b0db94bde0c0c7dfdea59c">XV_HDMIRX1_AUD_STA_3DAUD_CH_SHIFT</a>&#160;&#160;&#160;10</td></tr>
<tr class="memdesc:af5e43e9852b0db94bde0c0c7dfdea59c"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Audio channel Shift.  <a href="#af5e43e9852b0db94bde0c0c7dfdea59c">More...</a><br/></td></tr>
<tr class="separator:af5e43e9852b0db94bde0c0c7dfdea59c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7e8588bbc122639c1a31d79fe1c5b741"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7e8588bbc122639c1a31d79fe1c5b741">XV_HDMIRX1_AUD_STA_AUD_FMT_MASK</a>&#160;&#160;&#160;0x07</td></tr>
<tr class="memdesc:a7e8588bbc122639c1a31d79fe1c5b741"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Audio Format mask.  <a href="#a7e8588bbc122639c1a31d79fe1c5b741">More...</a><br/></td></tr>
<tr class="separator:a7e8588bbc122639c1a31d79fe1c5b741"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a630912a72ec9e1a8a04bbe43f03637e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a630912a72ec9e1a8a04bbe43f03637e9">XV_HDMIRX1_AUD_STA_AUD_FMT_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:a630912a72ec9e1a8a04bbe43f03637e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Audio Format Shift.  <a href="#a630912a72ec9e1a8a04bbe43f03637e9">More...</a><br/></td></tr>
<tr class="separator:a630912a72ec9e1a8a04bbe43f03637e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0890e7e5521f5fcd3ef91bef2426ba42"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a0890e7e5521f5fcd3ef91bef2426ba42">XV_HDMIRX1_AUD_STA_ACR_UPD_MASK</a>&#160;&#160;&#160;(1&lt;&lt;9)</td></tr>
<tr class="memdesc:a0890e7e5521f5fcd3ef91bef2426ba42"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status ACR Update mask.  <a href="#a0890e7e5521f5fcd3ef91bef2426ba42">More...</a><br/></td></tr>
<tr class="separator:a0890e7e5521f5fcd3ef91bef2426ba42"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1414ccd756a611744cbfe8bb88e16f48"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1414ccd756a611744cbfe8bb88e16f48">XV_HDMIRX1_LNKSTA_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(0*4))</td></tr>
<tr class="memdesc:a1414ccd756a611744cbfe8bb88e16f48"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Identification Register offset.  <a href="#a1414ccd756a611744cbfe8bb88e16f48">More...</a><br/></td></tr>
<tr class="separator:a1414ccd756a611744cbfe8bb88e16f48"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7a69f20270689c5abfbee2b0db6cc7a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7a69f20270689c5abfbee2b0db6cc7a0">XV_HDMIRX1_LNKSTA_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(1*4))</td></tr>
<tr class="memdesc:a7a69f20270689c5abfbee2b0db6cc7a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Control Register offset.  <a href="#a7a69f20270689c5abfbee2b0db6cc7a0">More...</a><br/></td></tr>
<tr class="separator:a7a69f20270689c5abfbee2b0db6cc7a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a23eec7113adc6c29ad2a46331582ae29"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a23eec7113adc6c29ad2a46331582ae29">XV_HDMIRX1_LNKSTA_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(2*4))</td></tr>
<tr class="memdesc:a23eec7113adc6c29ad2a46331582ae29"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Control Register Set offset.  <a href="#a23eec7113adc6c29ad2a46331582ae29">More...</a><br/></td></tr>
<tr class="separator:a23eec7113adc6c29ad2a46331582ae29"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0ea4dac580c41d65c59984742c93fcaf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a0ea4dac580c41d65c59984742c93fcaf">XV_HDMIRX1_LNKSTA_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(3*4))</td></tr>
<tr class="memdesc:a0ea4dac580c41d65c59984742c93fcaf"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Control Register Clear offset.  <a href="#a0ea4dac580c41d65c59984742c93fcaf">More...</a><br/></td></tr>
<tr class="separator:a0ea4dac580c41d65c59984742c93fcaf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae1aaa652d8211c7cc612dd506aeb480d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae1aaa652d8211c7cc612dd506aeb480d">XV_HDMIRX1_LNKSTA_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(4*4))</td></tr>
<tr class="memdesc:ae1aaa652d8211c7cc612dd506aeb480d"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Status Register offset.  <a href="#ae1aaa652d8211c7cc612dd506aeb480d">More...</a><br/></td></tr>
<tr class="separator:ae1aaa652d8211c7cc612dd506aeb480d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a87138c8927cdc27db845edb3556a82c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a87138c8927cdc27db845edb3556a82c8">XV_HDMIRX1_LNKSTA_LNK_ERR0_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(5*4))</td></tr>
<tr class="memdesc:a87138c8927cdc27db845edb3556a82c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Link Error Counter Channel 0 Register offset.  <a href="#a87138c8927cdc27db845edb3556a82c8">More...</a><br/></td></tr>
<tr class="separator:a87138c8927cdc27db845edb3556a82c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5d7731b44b7ab0d771dcf9864b45c470"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a5d7731b44b7ab0d771dcf9864b45c470">XV_HDMIRX1_LNKSTA_LNK_ERR1_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(6*4))</td></tr>
<tr class="memdesc:a5d7731b44b7ab0d771dcf9864b45c470"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Link Error Counter Channel 1 Register offset.  <a href="#a5d7731b44b7ab0d771dcf9864b45c470">More...</a><br/></td></tr>
<tr class="separator:a5d7731b44b7ab0d771dcf9864b45c470"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a98ae4b2e8422beaf711f1c9549a21851"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a98ae4b2e8422beaf711f1c9549a21851">XV_HDMIRX1_LNKSTA_LNK_ERR2_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(7*4))</td></tr>
<tr class="memdesc:a98ae4b2e8422beaf711f1c9549a21851"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Link Error Counter Channel 2 Register offset.  <a href="#a98ae4b2e8422beaf711f1c9549a21851">More...</a><br/></td></tr>
<tr class="separator:a98ae4b2e8422beaf711f1c9549a21851"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af3377eb2df940c5697d67f58e08cd20f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af3377eb2df940c5697d67f58e08cd20f">XV_HDMIRX1_PKT_ECC_ERR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(8*4))</td></tr>
<tr class="memdesc:af3377eb2df940c5697d67f58e08cd20f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Packet ECC Error Register offset.  <a href="#af3377eb2df940c5697d67f58e08cd20f">More...</a><br/></td></tr>
<tr class="separator:af3377eb2df940c5697d67f58e08cd20f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad74412e1cce4c05dc20962e823caaa2e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad74412e1cce4c05dc20962e823caaa2e">XV_HDMIRX1_TRIB_ANLZ_TIM_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(9*4))</td></tr>
<tr class="memdesc:ad74412e1cce4c05dc20962e823caaa2e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte Analyzer Timing Register offset.  <a href="#ad74412e1cce4c05dc20962e823caaa2e">More...</a><br/></td></tr>
<tr class="separator:ad74412e1cce4c05dc20962e823caaa2e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8ecc8705595c3f5ef2efdefea908ef19"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a8ecc8705595c3f5ef2efdefea908ef19">XV_HDMIRX1_TRIB_HBP_HS_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(10*4))</td></tr>
<tr class="memdesc:a8ecc8705595c3f5ef2efdefea908ef19"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte HBP_HS Register offset.  <a href="#a8ecc8705595c3f5ef2efdefea908ef19">More...</a><br/></td></tr>
<tr class="separator:a8ecc8705595c3f5ef2efdefea908ef19"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af450e13abf1a60b31de267c985fffbaa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af450e13abf1a60b31de267c985fffbaa">XV_HDMIRX1_TRIB_ANLZ_LN_ACT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(11*4))</td></tr>
<tr class="memdesc:af450e13abf1a60b31de267c985fffbaa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte Analyzer Line Size Register offset.  <a href="#af450e13abf1a60b31de267c985fffbaa">More...</a><br/></td></tr>
<tr class="separator:af450e13abf1a60b31de267c985fffbaa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4b0867e14c060bc025e48a9ad4fd4384"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a4b0867e14c060bc025e48a9ad4fd4384">XV_HDMIRX1_LNKSTA_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a4b0867e14c060bc025e48a9ad4fd4384"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Control Run mask.  <a href="#a4b0867e14c060bc025e48a9ad4fd4384">More...</a><br/></td></tr>
<tr class="separator:a4b0867e14c060bc025e48a9ad4fd4384"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae1e79cbc38e074f009b92ccb96660faf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ae1e79cbc38e074f009b92ccb96660faf">XV_HDMIRX1_LNKSTA_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:ae1e79cbc38e074f009b92ccb96660faf"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Control Interrupt Enable mask.  <a href="#ae1e79cbc38e074f009b92ccb96660faf">More...</a><br/></td></tr>
<tr class="separator:ae1e79cbc38e074f009b92ccb96660faf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adf40e22e8f2c99293f379a117807d84d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#adf40e22e8f2c99293f379a117807d84d">XV_HDMIRX1_LNKSTA_CTRL_ERR_CLR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:adf40e22e8f2c99293f379a117807d84d"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Control Error Clear mask.  <a href="#adf40e22e8f2c99293f379a117807d84d">More...</a><br/></td></tr>
<tr class="separator:adf40e22e8f2c99293f379a117807d84d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:affc58e86fdd9965c66c1787293747fe7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#affc58e86fdd9965c66c1787293747fe7">XV_HDMIRX1_LNKSTA_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:affc58e86fdd9965c66c1787293747fe7"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Status Interrupt mask.  <a href="#affc58e86fdd9965c66c1787293747fe7">More...</a><br/></td></tr>
<tr class="separator:affc58e86fdd9965c66c1787293747fe7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac8d20de61b9c7d747c78d766aeaec51c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac8d20de61b9c7d747c78d766aeaec51c">XV_HDMIRX1_LNKSTA_STA_ERR_MAX_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:ac8d20de61b9c7d747c78d766aeaec51c"><td class="mdescLeft">&#160;</td><td class="mdescRight">LNKSTA Status Maximum Errors mask.  <a href="#ac8d20de61b9c7d747c78d766aeaec51c">More...</a><br/></td></tr>
<tr class="separator:ac8d20de61b9c7d747c78d766aeaec51c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5bbac44be7ff425765198c35f15ee990"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a5bbac44be7ff425765198c35f15ee990">XV_HDMIRX1_TRIB_ANLZ_TIM_CHGD_CNT_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a5bbac44be7ff425765198c35f15ee990"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte analyzer timing changed count mask.  <a href="#a5bbac44be7ff425765198c35f15ee990">More...</a><br/></td></tr>
<tr class="separator:a5bbac44be7ff425765198c35f15ee990"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad90bee32417f21768fc9b165ef2b39e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad90bee32417f21768fc9b165ef2b39e1">XV_HDMIRX1_TRIB_ANLZ_TIM_CHGD_CNT_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ad90bee32417f21768fc9b165ef2b39e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte analyzer timing changed count shift.  <a href="#ad90bee32417f21768fc9b165ef2b39e1">More...</a><br/></td></tr>
<tr class="separator:ad90bee32417f21768fc9b165ef2b39e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aefd7163342d38fe7440ac8cb178bb734"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aefd7163342d38fe7440ac8cb178bb734">XV_HDMIRX1_TRIB_ANLZ_TIM_VS_POL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;16)</td></tr>
<tr class="memdesc:aefd7163342d38fe7440ac8cb178bb734"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte analyzer timing vsync polarity mask.  <a href="#aefd7163342d38fe7440ac8cb178bb734">More...</a><br/></td></tr>
<tr class="separator:aefd7163342d38fe7440ac8cb178bb734"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a25030374b218ae27a165342023eb26f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a25030374b218ae27a165342023eb26f6">XV_HDMIRX1_TRIB_ANLZ_TIM_HS_POL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;17)</td></tr>
<tr class="memdesc:a25030374b218ae27a165342023eb26f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte analyzer timing hsync polarity mask.  <a href="#a25030374b218ae27a165342023eb26f6">More...</a><br/></td></tr>
<tr class="separator:a25030374b218ae27a165342023eb26f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a08ce749b52f9176223488d5436c10d2a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a08ce749b52f9176223488d5436c10d2a">XV_HDMIRX1_TRIB_HBP_HS_HS_SZ_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a08ce749b52f9176223488d5436c10d2a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte hsync size shift.  <a href="#a08ce749b52f9176223488d5436c10d2a">More...</a><br/></td></tr>
<tr class="separator:a08ce749b52f9176223488d5436c10d2a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a290b6094a24ee78187d80ce9e3bac2bf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a290b6094a24ee78187d80ce9e3bac2bf">XV_HDMIRX1_TRIB_HBP_HS_HS_SZ_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a290b6094a24ee78187d80ce9e3bac2bf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte hsync size mask.  <a href="#a290b6094a24ee78187d80ce9e3bac2bf">More...</a><br/></td></tr>
<tr class="separator:a290b6094a24ee78187d80ce9e3bac2bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac1ff018afd4c825fae5d24a0d99397c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac1ff018afd4c825fae5d24a0d99397c8">XV_HDMIRX1_TRIB_HBP_HS_HBP_SZ_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ac1ff018afd4c825fae5d24a0d99397c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte hbp size shift.  <a href="#ac1ff018afd4c825fae5d24a0d99397c8">More...</a><br/></td></tr>
<tr class="separator:ac1ff018afd4c825fae5d24a0d99397c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1cef14123da432543b502426ea4ba921"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1cef14123da432543b502426ea4ba921">XV_HDMIRX1_TRIB_HBP_HS_HBP_SZ_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a1cef14123da432543b502426ea4ba921"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte hbp size mask.  <a href="#a1cef14123da432543b502426ea4ba921">More...</a><br/></td></tr>
<tr class="separator:a1cef14123da432543b502426ea4ba921"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2e6a5f0f7a7eb7fd3ca5c02672995617"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a2e6a5f0f7a7eb7fd3ca5c02672995617">XV_HDMIRX1_TRIB_ANLZ_LN_ACT_ACT_SZ_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a2e6a5f0f7a7eb7fd3ca5c02672995617"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte analyzer act size shift.  <a href="#a2e6a5f0f7a7eb7fd3ca5c02672995617">More...</a><br/></td></tr>
<tr class="separator:a2e6a5f0f7a7eb7fd3ca5c02672995617"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a161cbe93ae2eadf4572c49ddac875dd9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a161cbe93ae2eadf4572c49ddac875dd9">XV_HDMIRX1_TRIB_ANLZ_LN_ACT_ACT_SZ_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a161cbe93ae2eadf4572c49ddac875dd9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte analyzer act size mask.  <a href="#a161cbe93ae2eadf4572c49ddac875dd9">More...</a><br/></td></tr>
<tr class="separator:a161cbe93ae2eadf4572c49ddac875dd9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aae138c58ab74045375d385644647ebf5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aae138c58ab74045375d385644647ebf5">XV_HDMIRX1_TRIB_ANLZ_LN_ACT_LN_SZ_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:aae138c58ab74045375d385644647ebf5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte analyzer line act shift.  <a href="#aae138c58ab74045375d385644647ebf5">More...</a><br/></td></tr>
<tr class="separator:aae138c58ab74045375d385644647ebf5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a117109a90e42e3017e55fbfc7ebd9966"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a117109a90e42e3017e55fbfc7ebd9966">XV_HDMIRX1_TRIB_ANLZ_LN_ACT_LN_SZ_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a117109a90e42e3017e55fbfc7ebd9966"><td class="mdescLeft">&#160;</td><td class="mdescRight">Tri-byte analyzer line act mask.  <a href="#a117109a90e42e3017e55fbfc7ebd9966">More...</a><br/></td></tr>
<tr class="separator:a117109a90e42e3017e55fbfc7ebd9966"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a00e5be7b31aa15206b65f39be3c3725b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a00e5be7b31aa15206b65f39be3c3725b">XV_HDMIRX1_FRL_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(0*4))</td></tr>
<tr class="memdesc:a00e5be7b31aa15206b65f39be3c3725b"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Identification Register offset.  <a href="#a00e5be7b31aa15206b65f39be3c3725b">More...</a><br/></td></tr>
<tr class="separator:a00e5be7b31aa15206b65f39be3c3725b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a75abb8243e3ab51c5be8507ea4e3dec8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a75abb8243e3ab51c5be8507ea4e3dec8">XV_HDMIRX1_FRL_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(1*4))</td></tr>
<tr class="memdesc:a75abb8243e3ab51c5be8507ea4e3dec8"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Register offset.  <a href="#a75abb8243e3ab51c5be8507ea4e3dec8">More...</a><br/></td></tr>
<tr class="separator:a75abb8243e3ab51c5be8507ea4e3dec8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a32a9590fef5f8526e7c68b2ce8e88f89"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a32a9590fef5f8526e7c68b2ce8e88f89">XV_HDMIRX1_FRL_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(2*4))</td></tr>
<tr class="memdesc:a32a9590fef5f8526e7c68b2ce8e88f89"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Register Set offset.  <a href="#a32a9590fef5f8526e7c68b2ce8e88f89">More...</a><br/></td></tr>
<tr class="separator:a32a9590fef5f8526e7c68b2ce8e88f89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a445d11205376c2220586ddd6c01fb423"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a445d11205376c2220586ddd6c01fb423">XV_HDMIRX1_FRL_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(3*4))</td></tr>
<tr class="memdesc:a445d11205376c2220586ddd6c01fb423"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Register Clear offset.  <a href="#a445d11205376c2220586ddd6c01fb423">More...</a><br/></td></tr>
<tr class="separator:a445d11205376c2220586ddd6c01fb423"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a96860e2915010d82971cc380b30d30fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a96860e2915010d82971cc380b30d30fd">XV_HDMIRX1_FRL_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(4*4))</td></tr>
<tr class="memdesc:a96860e2915010d82971cc380b30d30fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Register offset.  <a href="#a96860e2915010d82971cc380b30d30fd">More...</a><br/></td></tr>
<tr class="separator:a96860e2915010d82971cc380b30d30fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a32129335b27ab577af25798959eafb6a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a32129335b27ab577af25798959eafb6a">XV_HDMIRX1_FRL_VCLK_VCKE_RATIO_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(7*4))</td></tr>
<tr class="memdesc:a32129335b27ab577af25798959eafb6a"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Video Clock to VCKE Ratio Register offset.  <a href="#a32129335b27ab577af25798959eafb6a">More...</a><br/></td></tr>
<tr class="separator:a32129335b27ab577af25798959eafb6a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa5500d41f17295752a46f34a3f6ca2f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa5500d41f17295752a46f34a3f6ca2f3">XV_HDMIRX1_FRL_SCDC_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(8*4))</td></tr>
<tr class="memdesc:aa5500d41f17295752a46f34a3f6ca2f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Video Clock Register offset.  <a href="#aa5500d41f17295752a46f34a3f6ca2f3">More...</a><br/></td></tr>
<tr class="separator:aa5500d41f17295752a46f34a3f6ca2f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9607aefecf7958adf00b11faaca7ceb0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a9607aefecf7958adf00b11faaca7ceb0">XV_HDMIRX1_FRL_RATIO_TOT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(9*4))</td></tr>
<tr class="memdesc:a9607aefecf7958adf00b11faaca7ceb0"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Total Data Register offset.  <a href="#a9607aefecf7958adf00b11faaca7ceb0">More...</a><br/></td></tr>
<tr class="separator:a9607aefecf7958adf00b11faaca7ceb0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a5393b88617a33dff7527a0c7a3f84c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a1a5393b88617a33dff7527a0c7a3f84c">XV_HDMIRX1_FRL_RATIO_ACT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(10*4))</td></tr>
<tr class="memdesc:a1a5393b88617a33dff7527a0c7a3f84c"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Total Active Data Register offset.  <a href="#a1a5393b88617a33dff7527a0c7a3f84c">More...</a><br/></td></tr>
<tr class="separator:a1a5393b88617a33dff7527a0c7a3f84c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a95df122fd8f593ac94504abaff87fecb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a95df122fd8f593ac94504abaff87fecb">XV_HDMIRX1_FRL_RSFC_CNT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(11*4))</td></tr>
<tr class="memdesc:a95df122fd8f593ac94504abaff87fecb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reed-Solomon FEC Counter Data Register offset.  <a href="#a95df122fd8f593ac94504abaff87fecb">More...</a><br/></td></tr>
<tr class="separator:a95df122fd8f593ac94504abaff87fecb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a566bd6a5e931c701ab04941f556b7817"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a566bd6a5e931c701ab04941f556b7817">XV_HDMIRX1_FRL_ERR_CNT1_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(12*4))</td></tr>
<tr class="memdesc:a566bd6a5e931c701ab04941f556b7817"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Error Count Data Register offset.  <a href="#a566bd6a5e931c701ab04941f556b7817">More...</a><br/></td></tr>
<tr class="separator:a566bd6a5e931c701ab04941f556b7817"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a49b8c41fcbbd455844d641a215d6eae8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a49b8c41fcbbd455844d641a215d6eae8">XV_HDMIRX1_FRL_VID_LOCK_CNT_OFFSET</a>&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(13*4))</td></tr>
<tr class="memdesc:a49b8c41fcbbd455844d641a215d6eae8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Video Lock Count Data Register offset.  <a href="#a49b8c41fcbbd455844d641a215d6eae8">More...</a><br/></td></tr>
<tr class="separator:a49b8c41fcbbd455844d641a215d6eae8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a21d52c1e98512bf55931aba594323451"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a21d52c1e98512bf55931aba594323451">XV_HDMIRX1_FRL_CTRL_RSTN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a21d52c1e98512bf55931aba594323451"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Resetn mask.  <a href="#a21d52c1e98512bf55931aba594323451">More...</a><br/></td></tr>
<tr class="separator:a21d52c1e98512bf55931aba594323451"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7649d0a19aea029fbe8aa66aa2e7bb3f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7649d0a19aea029fbe8aa66aa2e7bb3f">XV_HDMIRX1_FRL_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a7649d0a19aea029fbe8aa66aa2e7bb3f"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Interrupt Enable mask.  <a href="#a7649d0a19aea029fbe8aa66aa2e7bb3f">More...</a><br/></td></tr>
<tr class="separator:a7649d0a19aea029fbe8aa66aa2e7bb3f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aad30ea73982fde5380a2833d81232f77"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aad30ea73982fde5380a2833d81232f77">XV_HDMIRX1_FRL_CTRL_CLK_RATIO_UPD_EVT_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:aad30ea73982fde5380a2833d81232f77"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Clock Ratio Update Event Enable mask.  <a href="#aad30ea73982fde5380a2833d81232f77">More...</a><br/></td></tr>
<tr class="separator:aad30ea73982fde5380a2833d81232f77"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a98140ad3ebfd81ea887155d70d27944f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a98140ad3ebfd81ea887155d70d27944f">XV_HDMIRX1_FRL_CTRL_SKEW_EVT_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a98140ad3ebfd81ea887155d70d27944f"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Skew Event Enable mask.  <a href="#a98140ad3ebfd81ea887155d70d27944f">More...</a><br/></td></tr>
<tr class="separator:a98140ad3ebfd81ea887155d70d27944f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac0543cd5347f0876ed999cf7fbe6bb0c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac0543cd5347f0876ed999cf7fbe6bb0c">XV_HDMIRX1_FRL_CTRL_RSCC_RSFC_DISP_CLR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:ac0543cd5347f0876ed999cf7fbe6bb0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL RSCC Disparity Clear mask.  <a href="#ac0543cd5347f0876ed999cf7fbe6bb0c">More...</a><br/></td></tr>
<tr class="separator:ac0543cd5347f0876ed999cf7fbe6bb0c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa929db9fe8649faf5c094fb703fd82f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa929db9fe8649faf5c094fb703fd82f9">XV_HDMIRX1_FRL_CTRL_FLT_CLR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:aa929db9fe8649faf5c094fb703fd82f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control FLT Clear mask.  <a href="#aa929db9fe8649faf5c094fb703fd82f9">More...</a><br/></td></tr>
<tr class="separator:aa929db9fe8649faf5c094fb703fd82f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a529c5fbb5a5dbc3e6b133550576b915d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a529c5fbb5a5dbc3e6b133550576b915d">XV_HDMIRX1_FRL_CTRL_FRL_RATE_WR_EVT_EN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;14)</td></tr>
<tr class="memdesc:a529c5fbb5a5dbc3e6b133550576b915d"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control FRL Rate Write Event Enable.  <a href="#a529c5fbb5a5dbc3e6b133550576b915d">More...</a><br/></td></tr>
<tr class="separator:a529c5fbb5a5dbc3e6b133550576b915d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6df54e050460b99271edf151b9ad0f0d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a6df54e050460b99271edf151b9ad0f0d">XV_HDMIRX1_FRL_CTRL_DPACK_RST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;15)</td></tr>
<tr class="memdesc:a6df54e050460b99271edf151b9ad0f0d"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control DPACK Reset mask.  <a href="#a6df54e050460b99271edf151b9ad0f0d">More...</a><br/></td></tr>
<tr class="separator:a6df54e050460b99271edf151b9ad0f0d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a754c0697e23ed8df25ce37bbafb354fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a754c0697e23ed8df25ce37bbafb354fd">XV_HDMIRX1_FRL_CTRL_DPACK_ERR_CNT_CLR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;16)</td></tr>
<tr class="memdesc:a754c0697e23ed8df25ce37bbafb354fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control DPACK Error Counter Clear mask.  <a href="#a754c0697e23ed8df25ce37bbafb354fd">More...</a><br/></td></tr>
<tr class="separator:a754c0697e23ed8df25ce37bbafb354fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a71db0925746b66864611a70e65445328"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a71db0925746b66864611a70e65445328">XV_HDMIRX1_FRL_CTRL_DPACK_AUTO_RST_DIS_MASK</a>&#160;&#160;&#160;(1&lt;&lt;17)</td></tr>
<tr class="memdesc:a71db0925746b66864611a70e65445328"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control DPACK Auto Reset Disable mask.  <a href="#a71db0925746b66864611a70e65445328">More...</a><br/></td></tr>
<tr class="separator:a71db0925746b66864611a70e65445328"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad4103d12ed12bd574602c02a0a5b300e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad4103d12ed12bd574602c02a0a5b300e">XV_HDMIRX1_FRL_CTRL_VID_LOCK_CNT_CLR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;18)</td></tr>
<tr class="memdesc:ad4103d12ed12bd574602c02a0a5b300e"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Video Lock Counter Clear Mask.  <a href="#ad4103d12ed12bd574602c02a0a5b300e">More...</a><br/></td></tr>
<tr class="separator:ad4103d12ed12bd574602c02a0a5b300e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2ddbe9d9d80c511a34e8f581f467bf69"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a2ddbe9d9d80c511a34e8f581f467bf69">XV_HDMIRX1_FRL_CTRL_VID_LOCK_RST_DIS_MASK</a>&#160;&#160;&#160;(1&lt;&lt;19)</td></tr>
<tr class="memdesc:a2ddbe9d9d80c511a34e8f581f467bf69"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control Video Lock Reset Disable Mask.  <a href="#a2ddbe9d9d80c511a34e8f581f467bf69">More...</a><br/></td></tr>
<tr class="separator:a2ddbe9d9d80c511a34e8f581f467bf69"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afa179bd6d9cac676f9b7df1ee8ffd205"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#afa179bd6d9cac676f9b7df1ee8ffd205">XV_HDMIRX1_FRL_CTRL_FLT_THRES_MASK</a>&#160;&#160;&#160;0xFF</td></tr>
<tr class="memdesc:afa179bd6d9cac676f9b7df1ee8ffd205"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Control FLT Threshold mask.  <a href="#afa179bd6d9cac676f9b7df1ee8ffd205">More...</a><br/></td></tr>
<tr class="separator:afa179bd6d9cac676f9b7df1ee8ffd205"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6bc624e0b0602449534d016b66261420"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a6bc624e0b0602449534d016b66261420">XV_HDMIRX1_FRL_CTRL_FLT_THRES_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:a6bc624e0b0602449534d016b66261420"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Config LTP Threshold shift.  <a href="#a6bc624e0b0602449534d016b66261420">More...</a><br/></td></tr>
<tr class="separator:a6bc624e0b0602449534d016b66261420"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a19aa4846875e36f3df281003be17365b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a19aa4846875e36f3df281003be17365b">XV_HDMIRX1_FRL_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a19aa4846875e36f3df281003be17365b"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Interrupt mask.  <a href="#a19aa4846875e36f3df281003be17365b">More...</a><br/></td></tr>
<tr class="separator:a19aa4846875e36f3df281003be17365b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a026e659775cddab20ce2b7127d886187"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a026e659775cddab20ce2b7127d886187">XV_HDMIRX1_FRL_STA_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a026e659775cddab20ce2b7127d886187"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Event mask.  <a href="#a026e659775cddab20ce2b7127d886187">More...</a><br/></td></tr>
<tr class="separator:a026e659775cddab20ce2b7127d886187"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2721fcb8496d097ab7cf21f2f39290b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a2721fcb8496d097ab7cf21f2f39290b4">XV_HDMIRX1_FRL_STA_FLT_PM_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a2721fcb8496d097ab7cf21f2f39290b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status FLT Pattern Match event mask.  <a href="#a2721fcb8496d097ab7cf21f2f39290b4">More...</a><br/></td></tr>
<tr class="separator:a2721fcb8496d097ab7cf21f2f39290b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7ddf3b09dbf2981e2dd320fdb3fd3115"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a7ddf3b09dbf2981e2dd320fdb3fd3115">XV_HDMIRX1_FRL_STA_FLT_PM_ALLL_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:a7ddf3b09dbf2981e2dd320fdb3fd3115"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status FLT Pattern Match All Lanes mask.  <a href="#a7ddf3b09dbf2981e2dd320fdb3fd3115">More...</a><br/></td></tr>
<tr class="separator:a7ddf3b09dbf2981e2dd320fdb3fd3115"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a290ac811254db762d363a1f1a69e23d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a290ac811254db762d363a1f1a69e23d3">XV_HDMIRX1_FRL_STA_FLT_PM_ALLL_SHIFT</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:a290ac811254db762d363a1f1a69e23d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status FLT Pattern Match All Lanes shift.  <a href="#a290ac811254db762d363a1f1a69e23d3">More...</a><br/></td></tr>
<tr class="separator:a290ac811254db762d363a1f1a69e23d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa09e7df816b5b21cfd051bbaf0b43fe2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa09e7df816b5b21cfd051bbaf0b43fe2">XV_HDMIRX1_FRL_STA_FLT_PM_L0_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:aa09e7df816b5b21cfd051bbaf0b43fe2"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status FLT Pattern Match Lane 0 mask.  <a href="#aa09e7df816b5b21cfd051bbaf0b43fe2">More...</a><br/></td></tr>
<tr class="separator:aa09e7df816b5b21cfd051bbaf0b43fe2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adf6d5682c4c2464afc7f56546fb48180"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#adf6d5682c4c2464afc7f56546fb48180">XV_HDMIRX1_FRL_STA_FLT_PM_L1_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:adf6d5682c4c2464afc7f56546fb48180"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status FLT Pattern Match Lane 0 mask.  <a href="#adf6d5682c4c2464afc7f56546fb48180">More...</a><br/></td></tr>
<tr class="separator:adf6d5682c4c2464afc7f56546fb48180"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5f9b94d9a17d07164465effd3babde35"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a5f9b94d9a17d07164465effd3babde35">XV_HDMIRX1_FRL_STA_FLT_PM_L2_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:a5f9b94d9a17d07164465effd3babde35"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status FLT Pattern Match Lane 0 mask.  <a href="#a5f9b94d9a17d07164465effd3babde35">More...</a><br/></td></tr>
<tr class="separator:a5f9b94d9a17d07164465effd3babde35"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaa7457d835c11acfbdcd51a04fd69612"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aaa7457d835c11acfbdcd51a04fd69612">XV_HDMIRX1_FRL_STA_FLT_PM_L3_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:aaa7457d835c11acfbdcd51a04fd69612"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status FLT Pattern Match Lane 0 mask.  <a href="#aaa7457d835c11acfbdcd51a04fd69612">More...</a><br/></td></tr>
<tr class="separator:aaa7457d835c11acfbdcd51a04fd69612"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9d7548c9ae36cafd37124871aa47f809"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a9d7548c9ae36cafd37124871aa47f809">XV_HDMIRX1_FRL_STA_FLT_UPD_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:a9d7548c9ae36cafd37124871aa47f809"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status FLT Update event mask.  <a href="#a9d7548c9ae36cafd37124871aa47f809">More...</a><br/></td></tr>
<tr class="separator:a9d7548c9ae36cafd37124871aa47f809"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac2fe661649f7abaca976e6655434f059"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac2fe661649f7abaca976e6655434f059">XV_HDMIRX1_FRL_STA_RATE_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:ac2fe661649f7abaca976e6655434f059"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status FRL Rate change event mask.  <a href="#ac2fe661649f7abaca976e6655434f059">More...</a><br/></td></tr>
<tr class="separator:ac2fe661649f7abaca976e6655434f059"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab77c50ec8738b12eb34bfcc973d84b18"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab77c50ec8738b12eb34bfcc973d84b18">XV_HDMIRX1_FRL_STA_LANE_LOCK_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;9)</td></tr>
<tr class="memdesc:ab77c50ec8738b12eb34bfcc973d84b18"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Lane Lock event mask.  <a href="#ab77c50ec8738b12eb34bfcc973d84b18">More...</a><br/></td></tr>
<tr class="separator:ab77c50ec8738b12eb34bfcc973d84b18"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab95cf4e9c8b7891357d146db4f17c12c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab95cf4e9c8b7891357d146db4f17c12c">XV_HDMIRX1_FRL_STA_CLK_RATIO_UPD_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;10)</td></tr>
<tr class="memdesc:ab95cf4e9c8b7891357d146db4f17c12c"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Clock Ratio Update event mask.  <a href="#ab95cf4e9c8b7891357d146db4f17c12c">More...</a><br/></td></tr>
<tr class="separator:ab95cf4e9c8b7891357d146db4f17c12c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adff37a259608df74837cd1854e1a7cd6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#adff37a259608df74837cd1854e1a7cd6">XV_HDMIRX1_FRL_STA_SKEW_LOCK_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;11)</td></tr>
<tr class="memdesc:adff37a259608df74837cd1854e1a7cd6"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Skew Lock event mask.  <a href="#adff37a259608df74837cd1854e1a7cd6">More...</a><br/></td></tr>
<tr class="separator:adff37a259608df74837cd1854e1a7cd6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a14fa43a8eb929f9834823a037557c755"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a14fa43a8eb929f9834823a037557c755">XV_HDMIRX1_FRL_STA_LANE_LOCK_ALLL_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:a14fa43a8eb929f9834823a037557c755"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Lane Lock All Lanes mask.  <a href="#a14fa43a8eb929f9834823a037557c755">More...</a><br/></td></tr>
<tr class="separator:a14fa43a8eb929f9834823a037557c755"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af3ce4c26d43187cdd23935f92d00772b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af3ce4c26d43187cdd23935f92d00772b">XV_HDMIRX1_FRL_STA_LANE_LOCK_ALLL_SHIFT</a>&#160;&#160;&#160;12</td></tr>
<tr class="memdesc:af3ce4c26d43187cdd23935f92d00772b"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Lane Lock All Lanes shift.  <a href="#af3ce4c26d43187cdd23935f92d00772b">More...</a><br/></td></tr>
<tr class="separator:af3ce4c26d43187cdd23935f92d00772b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aefb851bc82ac01da4415eec7f0652c84"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aefb851bc82ac01da4415eec7f0652c84">XV_HDMIRX1_FRL_STA_LANE_LOCK_L0_MASK</a>&#160;&#160;&#160;(1&lt;&lt;12)</td></tr>
<tr class="memdesc:aefb851bc82ac01da4415eec7f0652c84"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Lane Lock L0 mask.  <a href="#aefb851bc82ac01da4415eec7f0652c84">More...</a><br/></td></tr>
<tr class="separator:aefb851bc82ac01da4415eec7f0652c84"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af7d24396f309b46e0d89a3c5d3e6bfa5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#af7d24396f309b46e0d89a3c5d3e6bfa5">XV_HDMIRX1_FRL_STA_LANE_LOCK_L1_MASK</a>&#160;&#160;&#160;(1&lt;&lt;13)</td></tr>
<tr class="memdesc:af7d24396f309b46e0d89a3c5d3e6bfa5"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Lane Lock L1 mask.  <a href="#af7d24396f309b46e0d89a3c5d3e6bfa5">More...</a><br/></td></tr>
<tr class="separator:af7d24396f309b46e0d89a3c5d3e6bfa5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac8efacae8a57dca401f42c4f5f093efc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac8efacae8a57dca401f42c4f5f093efc">XV_HDMIRX1_FRL_STA_LANE_LOCK_L2_MASK</a>&#160;&#160;&#160;(1&lt;&lt;14)</td></tr>
<tr class="memdesc:ac8efacae8a57dca401f42c4f5f093efc"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Lane Lock L2 mask.  <a href="#ac8efacae8a57dca401f42c4f5f093efc">More...</a><br/></td></tr>
<tr class="separator:ac8efacae8a57dca401f42c4f5f093efc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a313a043679a0f8d94e34fa616a70b113"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a313a043679a0f8d94e34fa616a70b113">XV_HDMIRX1_FRL_STA_LANE_LOCK_L3_MASK</a>&#160;&#160;&#160;(1&lt;&lt;15)</td></tr>
<tr class="memdesc:a313a043679a0f8d94e34fa616a70b113"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Lane Lock L3 mask.  <a href="#a313a043679a0f8d94e34fa616a70b113">More...</a><br/></td></tr>
<tr class="separator:a313a043679a0f8d94e34fa616a70b113"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa4a2f8e85cba03c8b0eb1a230b2f89c4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa4a2f8e85cba03c8b0eb1a230b2f89c4">XV_HDMIRX1_FRL_STA_WA_LOCK_ALLL_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:aa4a2f8e85cba03c8b0eb1a230b2f89c4"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Aligner Lock All Lanes mask.  <a href="#aa4a2f8e85cba03c8b0eb1a230b2f89c4">More...</a><br/></td></tr>
<tr class="separator:aa4a2f8e85cba03c8b0eb1a230b2f89c4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a55c84609819cd4f182160813cff62ffe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a55c84609819cd4f182160813cff62ffe">XV_HDMIRX1_FRL_STA_WA_LOCK_ALLL_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a55c84609819cd4f182160813cff62ffe"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Aligner Lock All Lanes shift.  <a href="#a55c84609819cd4f182160813cff62ffe">More...</a><br/></td></tr>
<tr class="separator:a55c84609819cd4f182160813cff62ffe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a05fb5edf2d95d4aaebecae4d77f1a7ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a05fb5edf2d95d4aaebecae4d77f1a7ff">XV_HDMIRX1_FRL_STA_WA_LOCK_L0_MASK</a>&#160;&#160;&#160;(1&lt;&lt;16)</td></tr>
<tr class="memdesc:a05fb5edf2d95d4aaebecae4d77f1a7ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Aligner Lock L0 mask.  <a href="#a05fb5edf2d95d4aaebecae4d77f1a7ff">More...</a><br/></td></tr>
<tr class="separator:a05fb5edf2d95d4aaebecae4d77f1a7ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a863a347d86204ae241caf3b75dc830bc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a863a347d86204ae241caf3b75dc830bc">XV_HDMIRX1_FRL_STA_WA_LOCK_L1_MASK</a>&#160;&#160;&#160;(1&lt;&lt;17)</td></tr>
<tr class="memdesc:a863a347d86204ae241caf3b75dc830bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Aligner Lock L1 mask.  <a href="#a863a347d86204ae241caf3b75dc830bc">More...</a><br/></td></tr>
<tr class="separator:a863a347d86204ae241caf3b75dc830bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9617a7728c0e6c52f9570d425785633c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a9617a7728c0e6c52f9570d425785633c">XV_HDMIRX1_FRL_STA_WA_LOCK_L2_MASK</a>&#160;&#160;&#160;(1&lt;&lt;18)</td></tr>
<tr class="memdesc:a9617a7728c0e6c52f9570d425785633c"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Aligner Lock L2 mask.  <a href="#a9617a7728c0e6c52f9570d425785633c">More...</a><br/></td></tr>
<tr class="separator:a9617a7728c0e6c52f9570d425785633c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aae460de84f682e7c476c4475f38ca9e9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aae460de84f682e7c476c4475f38ca9e9">XV_HDMIRX1_FRL_STA_WA_LOCK_L3_MASK</a>&#160;&#160;&#160;(1&lt;&lt;19)</td></tr>
<tr class="memdesc:aae460de84f682e7c476c4475f38ca9e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Aligner Lock L3 mask.  <a href="#aae460de84f682e7c476c4475f38ca9e9">More...</a><br/></td></tr>
<tr class="separator:aae460de84f682e7c476c4475f38ca9e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a47ebab7f2a605e29b68f2121c1bde7d7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a47ebab7f2a605e29b68f2121c1bde7d7">XV_HDMIRX1_FRL_STA_SCRM_LOCK_ALLL_MASK</a>&#160;&#160;&#160;0xF</td></tr>
<tr class="memdesc:a47ebab7f2a605e29b68f2121c1bde7d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Scrambler All Lanes mask.  <a href="#a47ebab7f2a605e29b68f2121c1bde7d7">More...</a><br/></td></tr>
<tr class="separator:a47ebab7f2a605e29b68f2121c1bde7d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4fb39fe8225243a7a63b683cde0e772c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a4fb39fe8225243a7a63b683cde0e772c">XV_HDMIRX1_FRL_STA_SCRM_LOCK_ALLL_SHIFT</a>&#160;&#160;&#160;20</td></tr>
<tr class="memdesc:a4fb39fe8225243a7a63b683cde0e772c"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Scrambler All Lanes shift.  <a href="#a4fb39fe8225243a7a63b683cde0e772c">More...</a><br/></td></tr>
<tr class="separator:a4fb39fe8225243a7a63b683cde0e772c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a254e0b71e23d9491cd4a4c887439794c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a254e0b71e23d9491cd4a4c887439794c">XV_HDMIRX1_FRL_STA_SCRM_LOCK_L0_MASK</a>&#160;&#160;&#160;(1&lt;&lt;20)</td></tr>
<tr class="memdesc:a254e0b71e23d9491cd4a4c887439794c"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Scrambler Lock L0 mask.  <a href="#a254e0b71e23d9491cd4a4c887439794c">More...</a><br/></td></tr>
<tr class="separator:a254e0b71e23d9491cd4a4c887439794c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab4edf834fbe041b7d89216e566316313"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ab4edf834fbe041b7d89216e566316313">XV_HDMIRX1_FRL_STA_SCRM_LOCK_L1_MASK</a>&#160;&#160;&#160;(1&lt;&lt;21)</td></tr>
<tr class="memdesc:ab4edf834fbe041b7d89216e566316313"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Scrambler Lock L1 mask.  <a href="#ab4edf834fbe041b7d89216e566316313">More...</a><br/></td></tr>
<tr class="separator:ab4edf834fbe041b7d89216e566316313"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5f29ae4406b5f11ca0b5a1005e026b90"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a5f29ae4406b5f11ca0b5a1005e026b90">XV_HDMIRX1_FRL_STA_SCRM_LOCK_L2_MASK</a>&#160;&#160;&#160;(1&lt;&lt;22)</td></tr>
<tr class="memdesc:a5f29ae4406b5f11ca0b5a1005e026b90"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Scrambler Lock L2 mask.  <a href="#a5f29ae4406b5f11ca0b5a1005e026b90">More...</a><br/></td></tr>
<tr class="separator:a5f29ae4406b5f11ca0b5a1005e026b90"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a89957a40e34b71ee90216175c42e6c24"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a89957a40e34b71ee90216175c42e6c24">XV_HDMIRX1_FRL_STA_SCRM_LOCK_L3_MASK</a>&#160;&#160;&#160;(1&lt;&lt;23)</td></tr>
<tr class="memdesc:a89957a40e34b71ee90216175c42e6c24"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Scrambler Lock L3 mask.  <a href="#a89957a40e34b71ee90216175c42e6c24">More...</a><br/></td></tr>
<tr class="separator:a89957a40e34b71ee90216175c42e6c24"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa1fb32957e468cc337ac7ce5828a0b50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa1fb32957e468cc337ac7ce5828a0b50">XV_HDMIRX1_FRL_STA_SKEW_LOCK_MASK</a>&#160;&#160;&#160;(1&lt;&lt;24)</td></tr>
<tr class="memdesc:aa1fb32957e468cc337ac7ce5828a0b50"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Skew Lock mask.  <a href="#aa1fb32957e468cc337ac7ce5828a0b50">More...</a><br/></td></tr>
<tr class="separator:aa1fb32957e468cc337ac7ce5828a0b50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afdfa16dd3c11af7a70bf3743f3c5dbd3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#afdfa16dd3c11af7a70bf3743f3c5dbd3">XV_HDMIRX1_FRL_STA_STR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;25)</td></tr>
<tr class="memdesc:afdfa16dd3c11af7a70bf3743f3c5dbd3"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Video STR mask.  <a href="#afdfa16dd3c11af7a70bf3743f3c5dbd3">More...</a><br/></td></tr>
<tr class="separator:afdfa16dd3c11af7a70bf3743f3c5dbd3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abe2e332e4def7d78b9692fcfe5dceb3a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#abe2e332e4def7d78b9692fcfe5dceb3a">XV_HDMIRX1_FRL_STA_VID_LOCK_MASK</a>&#160;&#160;&#160;(1&lt;&lt;26)</td></tr>
<tr class="memdesc:abe2e332e4def7d78b9692fcfe5dceb3a"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Video Lock mask.  <a href="#abe2e332e4def7d78b9692fcfe5dceb3a">More...</a><br/></td></tr>
<tr class="separator:abe2e332e4def7d78b9692fcfe5dceb3a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2c5d7ff6904298bf55ccaa3ad1e52209"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a2c5d7ff6904298bf55ccaa3ad1e52209">XV_HDMIRX1_FRL_STA_FRL_MODE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;27)</td></tr>
<tr class="memdesc:a2c5d7ff6904298bf55ccaa3ad1e52209"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Mode mask.  <a href="#a2c5d7ff6904298bf55ccaa3ad1e52209">More...</a><br/></td></tr>
<tr class="separator:a2c5d7ff6904298bf55ccaa3ad1e52209"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a819ca83e4c0169868874dc344b97e0f9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a819ca83e4c0169868874dc344b97e0f9">XV_HDMIRX1_FRL_STA_FRL_LANES_MASK</a>&#160;&#160;&#160;(1&lt;&lt;28)</td></tr>
<tr class="memdesc:a819ca83e4c0169868874dc344b97e0f9"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Lanes mask.  <a href="#a819ca83e4c0169868874dc344b97e0f9">More...</a><br/></td></tr>
<tr class="separator:a819ca83e4c0169868874dc344b97e0f9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9ce5dbbe22e0e4254cec1e5c1e791b9e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a9ce5dbbe22e0e4254cec1e5c1e791b9e">XV_HDMIRX1_FRL_STA_FRL_RATE_MASK</a>&#160;&#160;&#160;0x7</td></tr>
<tr class="memdesc:a9ce5dbbe22e0e4254cec1e5c1e791b9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Rate mask.  <a href="#a9ce5dbbe22e0e4254cec1e5c1e791b9e">More...</a><br/></td></tr>
<tr class="separator:a9ce5dbbe22e0e4254cec1e5c1e791b9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9ae67cbce6039396d76e9fae77871960"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a9ae67cbce6039396d76e9fae77871960">XV_HDMIRX1_FRL_STA_FRL_RATE_SHIFT</a>&#160;&#160;&#160;29</td></tr>
<tr class="memdesc:a9ae67cbce6039396d76e9fae77871960"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Status Rate shift.  <a href="#a9ae67cbce6039396d76e9fae77871960">More...</a><br/></td></tr>
<tr class="separator:a9ae67cbce6039396d76e9fae77871960"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aece82a4f2fafedbae117e46849c8f40a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aece82a4f2fafedbae117e46849c8f40a">XV_HDMIRX1_FRL_LNK_CLK_MASK</a>&#160;&#160;&#160;0xFFFFF</td></tr>
<tr class="memdesc:aece82a4f2fafedbae117e46849c8f40a"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Link Clock mask.  <a href="#aece82a4f2fafedbae117e46849c8f40a">More...</a><br/></td></tr>
<tr class="separator:aece82a4f2fafedbae117e46849c8f40a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad3117961fb5f5cff41d33e2c0f35eecc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ad3117961fb5f5cff41d33e2c0f35eecc">XV_HDMIRX1_FRL_VID_CLK_MASK</a>&#160;&#160;&#160;0xFFFFF</td></tr>
<tr class="memdesc:ad3117961fb5f5cff41d33e2c0f35eecc"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL Video Clock mask.  <a href="#ad3117961fb5f5cff41d33e2c0f35eecc">More...</a><br/></td></tr>
<tr class="separator:ad3117961fb5f5cff41d33e2c0f35eecc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac5b57521457e46c5e347db1bd1d8ac28"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#ac5b57521457e46c5e347db1bd1d8ac28">XV_HDMIRX1_FRL_SCDC_ADDR_MASK</a>&#160;&#160;&#160;0xFF</td></tr>
<tr class="memdesc:ac5b57521457e46c5e347db1bd1d8ac28"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL SCDC Address Interrupt mask.  <a href="#ac5b57521457e46c5e347db1bd1d8ac28">More...</a><br/></td></tr>
<tr class="separator:ac5b57521457e46c5e347db1bd1d8ac28"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a642b2cfd71e9e2e80ed18b0ee2ce0674"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a642b2cfd71e9e2e80ed18b0ee2ce0674">XV_HDMIRX1_FRL_SCDC_ADDR_SHIFT</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:a642b2cfd71e9e2e80ed18b0ee2ce0674"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL SCDC Address Interrupt mask.  <a href="#a642b2cfd71e9e2e80ed18b0ee2ce0674">More...</a><br/></td></tr>
<tr class="separator:a642b2cfd71e9e2e80ed18b0ee2ce0674"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afc293c2e58cd8a42b857d83e4cb388b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#afc293c2e58cd8a42b857d83e4cb388b5">XV_HDMIRX1_FRL_SCDC_DAT_MASK</a>&#160;&#160;&#160;0xFF</td></tr>
<tr class="memdesc:afc293c2e58cd8a42b857d83e4cb388b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL SCDC Data mask.  <a href="#afc293c2e58cd8a42b857d83e4cb388b5">More...</a><br/></td></tr>
<tr class="separator:afc293c2e58cd8a42b857d83e4cb388b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a070a1c8c80d4f949700398f70e4c1184"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a070a1c8c80d4f949700398f70e4c1184">XV_HDMIRX1_FRL_SCDC_DAT_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:a070a1c8c80d4f949700398f70e4c1184"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL SCDC Data mask.  <a href="#a070a1c8c80d4f949700398f70e4c1184">More...</a><br/></td></tr>
<tr class="separator:a070a1c8c80d4f949700398f70e4c1184"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:affb659995dc3b980da1ecf2bea25f794"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#affb659995dc3b980da1ecf2bea25f794">XV_HDMIRX1_FRL_SCDC_WR_MASK</a>&#160;&#160;&#160;(1&lt;&lt;16)</td></tr>
<tr class="memdesc:affb659995dc3b980da1ecf2bea25f794"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL SCDC Write mask.  <a href="#affb659995dc3b980da1ecf2bea25f794">More...</a><br/></td></tr>
<tr class="separator:affb659995dc3b980da1ecf2bea25f794"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a96095a3a06333a80279343e58bd9a512"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a96095a3a06333a80279343e58bd9a512">XV_HDMIRX1_FRL_SCDC_RD_MASK</a>&#160;&#160;&#160;(1&lt;&lt;17)</td></tr>
<tr class="memdesc:a96095a3a06333a80279343e58bd9a512"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL SCDC Read mask.  <a href="#a96095a3a06333a80279343e58bd9a512">More...</a><br/></td></tr>
<tr class="separator:a96095a3a06333a80279343e58bd9a512"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa89cb22259109c7e37ef35afa705782a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa89cb22259109c7e37ef35afa705782a">XV_HDMIRX1_FRL_SCDC_RDY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;18)</td></tr>
<tr class="memdesc:aa89cb22259109c7e37ef35afa705782a"><td class="mdescLeft">&#160;</td><td class="mdescRight">FRL SCDC Ready mask.  <a href="#aa89cb22259109c7e37ef35afa705782a">More...</a><br/></td></tr>
<tr class="separator:aa89cb22259109c7e37ef35afa705782a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a44f9bde6a5097e3b1c287447e8292f87"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a44f9bde6a5097e3b1c287447e8292f87">XV_HDMIRX1_SHIFT_16</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a44f9bde6a5097e3b1c287447e8292f87"><td class="mdescLeft">&#160;</td><td class="mdescRight">16 shift value  <a href="#a44f9bde6a5097e3b1c287447e8292f87">More...</a><br/></td></tr>
<tr class="separator:a44f9bde6a5097e3b1c287447e8292f87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a090582e52a472f924918d70505f62b11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a090582e52a472f924918d70505f62b11">XV_HDMIRX1_MASK_16</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a090582e52a472f924918d70505f62b11"><td class="mdescLeft">&#160;</td><td class="mdescRight">16 bit mask value  <a href="#a090582e52a472f924918d70505f62b11">More...</a><br/></td></tr>
<tr class="separator:a090582e52a472f924918d70505f62b11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa303f116af14392fe13aebd0cc78a125"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#aa303f116af14392fe13aebd0cc78a125">XV_HDMIRX1_PIO_ID</a>&#160;&#160;&#160;0x2200</td></tr>
<tr class="memdesc:aa303f116af14392fe13aebd0cc78a125"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO ID.  <a href="#aa303f116af14392fe13aebd0cc78a125">More...</a><br/></td></tr>
<tr class="separator:aa303f116af14392fe13aebd0cc78a125"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register access macro definition</div></td></tr>
<tr class="memitem:a411e9845d9812a9370460df4d352d1e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a411e9845d9812a9370460df4d352d1e1">XV_HdmiRx1_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:a411e9845d9812a9370460df4d352d1e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Operations.  <a href="#a411e9845d9812a9370460df4d352d1e1">More...</a><br/></td></tr>
<tr class="separator:a411e9845d9812a9370460df4d352d1e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a80876cd6b8704c0ad0aa94767e6e9b67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a80876cd6b8704c0ad0aa94767e6e9b67">XV_HdmiRx1_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:a80876cd6b8704c0ad0aa94767e6e9b67"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Operations.  <a href="#a80876cd6b8704c0ad0aa94767e6e9b67">More...</a><br/></td></tr>
<tr class="separator:a80876cd6b8704c0ad0aa94767e6e9b67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a851cb0524c797d3ce8380b1c27b9a17f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f">XV_HdmiRx1_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;<a class="el" href="xv__hdmirx1__hw_8h.html#a411e9845d9812a9370460df4d352d1e1">XV_HdmiRx1_In32</a>((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:a851cb0524c797d3ce8380b1c27b9a17f"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads a value from a HDMI RX register.  <a href="#a851cb0524c797d3ce8380b1c27b9a17f">More...</a><br/></td></tr>
<tr class="separator:a851cb0524c797d3ce8380b1c27b9a17f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a949523423dffb540041a98a38e283cf8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8">XV_HdmiRx1_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;<a class="el" href="xv__hdmirx1__hw_8h.html#a80876cd6b8704c0ad0aa94767e6e9b67">XV_HdmiRx1_Out32</a>((BaseAddress) + (RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:a949523423dffb540041a98a38e283cf8"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes a value to a HDMI RX register.  <a href="#a949523423dffb540041a98a38e283cf8">More...</a><br/></td></tr>
<tr class="separator:a949523423dffb540041a98a38e283cf8"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="acebfc50acd8328e43d89fd4d297eb9b7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_CTRL_ACR_UPD_EVT_EN_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control ACR Update Event Enable mask. </p>

</div>
</div>
<a class="anchor" id="ac3b08fa2ae41be9a6904419b439d79f3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUD_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="ad9cead30e8cec1e057a5670382f85aac"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a10826337df9a2f1577909678bfeea831"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUD_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Register offset. </p>

</div>
</div>
<a class="anchor" id="a025c0ac63f58c4d1b532ce2c49cc168d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a6144291d33bdfd02d9077042fb6a5f0d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUD_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Register Set offset. </p>

</div>
</div>
<a class="anchor" id="a29e933929edb889a5cf22e2b358bcbd6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_CTS_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUD_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD CTS Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ad6862d6b700903b0fde41c14f49c56ef">XV_HdmiRx1_GetAcrCts()</a>.</p>

</div>
</div>
<a class="anchor" id="ae9b202d8c94989184154789ae50cf7e4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUD_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="aa108342fb6a7cb47e297368082ba4943"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_N_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUD_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD N Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ad372b661989dfb070a6931b88aadad86">XV_HdmiRx1_GetAcrN()</a>.</p>

</div>
</div>
<a class="anchor" id="a43a10555bb908231f981067b8551250f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_STA_3DAUD_CH_MASK&#160;&#160;&#160;0x07</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Audio channel mask. </p>

</div>
</div>
<a class="anchor" id="af5e43e9852b0db94bde0c0c7dfdea59c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_STA_3DAUD_CH_SHIFT&#160;&#160;&#160;10</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Audio channel Shift. </p>

</div>
</div>
<a class="anchor" id="a0890e7e5521f5fcd3ef91bef2426ba42"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_STA_ACR_UPD_MASK&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status ACR Update mask. </p>

</div>
</div>
<a class="anchor" id="a0764f4406426ea7680979d7cf13f5409"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_STA_ACT_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Event mask. </p>

</div>
</div>
<a class="anchor" id="a1379c3a28e0344be55fa32908b17626e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_STA_ACT_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Active mask. </p>

</div>
</div>
<a class="anchor" id="af462fd88e1f6c3e1e0015534b78014ee"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_STA_AUD_CH_MASK&#160;&#160;&#160;0x03</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Audio channel mask. </p>

</div>
</div>
<a class="anchor" id="a89a6281a9f59ff584150a1b43f0c2fec"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_STA_AUD_CH_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Audio channel Shift. </p>

</div>
</div>
<a class="anchor" id="a7e8588bbc122639c1a31d79fe1c5b741"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_STA_AUD_FMT_MASK&#160;&#160;&#160;0x07</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Audio Format mask. </p>

</div>
</div>
<a class="anchor" id="a630912a72ec9e1a8a04bbe43f03637e9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_STA_AUD_FMT_SHIFT&#160;&#160;&#160;6</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Audio Format Shift. </p>

</div>
</div>
<a class="anchor" id="a2af8b2bd0e80317e44eec5d45891d52b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_STA_CH_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Event mask. </p>

</div>
</div>
<a class="anchor" id="a9b671fa1d778ce26fb96731f95660999"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a6b471c291404420baf14808dc39da8e4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUD_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUD_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="add9bba9228d3f408182b26777c21aa2b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="a0b6e46c9f463bf6c605f76ccc61c9f32"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_CTRL_FSYNC_VRR_CH_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control FSync/VRR change event enable mask. </p>

</div>
</div>
<a class="anchor" id="a983626c618f59a68cb6ef736c9f6d28a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a1c5746fc42b80fb22a390f6bb5d61d1b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register offset. </p>

</div>
</div>
<a class="anchor" id="ac798bb32a30b17ca65d0f3371172963c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Run mask. </p>

</div>
</div>
<a class="anchor" id="ac751b5b5be3fe003fe43f056f292bbf0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register Set offset. </p>

</div>
</div>
<a class="anchor" id="ae86fb548d5cd48847264bd5b70b791b0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_DAT_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Data Register offset. </p>

</div>
</div>
<a class="anchor" id="a3ad16e42fdc47d009ff567cbf65d7ca0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_DYN_HDR_INFO_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE) + (10 * 4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Dynamic HDR Info offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aa8d5e2d39022661864bdf89e0fca6b3d">XV_HdmiRx1_DynHDR_GetInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ab0a5740fe6d10b7c283a683e745518cf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_DYN_HDR_MEMADDR_LSB_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE) + (12 * 4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Lower address Dynamic HDR Status offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aadab16501ebe113f3881aa7c7d2091f1">XV_HdmiRx1_DynHDR_SetAddr()</a>.</p>

</div>
</div>
<a class="anchor" id="a94fec423e8bda97ee8cf9a7939e55aa5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_DYN_HDR_MEMADDR_MSB_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE) + (13 * 4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Higher address Dynamic HDR Status offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aadab16501ebe113f3881aa7c7d2091f1">XV_HdmiRx1_DynHDR_SetAddr()</a>.</p>

</div>
</div>
<a class="anchor" id="add06acac6296880fa714d3265160890d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_DYN_HDR_STS_ERR_MASK&#160;&#160;&#160;(0x3 &lt;&lt; 1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Errors asserted while writing ot memory. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aa8d5e2d39022661864bdf89e0fca6b3d">XV_HdmiRx1_DynHDR_GetInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a52d316fb63d45bfdcd8def3b5503ef03"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_DYN_HDR_STS_GOF_MASK&#160;&#160;&#160;(1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Graphics Overlay Flag. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aa8d5e2d39022661864bdf89e0fca6b3d">XV_HdmiRx1_DynHDR_GetInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="abd7ef1376fabe26cb32ece3c4efa7450"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_DYN_HDR_STS_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE) + (11 * 4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Dynamic HDR Status offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aa8d5e2d39022661864bdf89e0fca6b3d">XV_HdmiRx1_DynHDR_GetInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a459e57839a799f6d970783e7e380a16f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_ACTIVE_MASK&#160;&#160;&#160;(1&lt;&lt;10)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC Active mask. </p>

</div>
</div>
<a class="anchor" id="ab1cc8a2ea931e8964a9da817be414b53"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_ENABLED_MASK&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC Enabled mask. </p>

</div>
</div>
<a class="anchor" id="a6a9349c7dacd7f66810c4d23192e0b15"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_MAX_REF_RATE_MASK&#160;&#160;&#160;(0xFF &lt;&lt; 24)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC FreeSync Maximum refresh rate mask. </p>

</div>
</div>
<a class="anchor" id="a9aca9ff422ac8a1889a2f61f7ff5e016"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_MIN_REF_RATE_MASK&#160;&#160;&#160;(0xFF &lt;&lt; 16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC FreeSync Minimum refresh rate mask. </p>

</div>
</div>
<a class="anchor" id="a12239713af1cb762261264aecd2db6db"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC Register offset. </p>

</div>
</div>
<a class="anchor" id="a96cb820fa92f0e5ce5ed55d757683f74"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_PRO_BRIGHT_CTRL_ACT_MASK&#160;&#160;&#160;(1&lt;&lt;12)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC Pro Brightness Control Active mask. </p>

</div>
</div>
<a class="anchor" id="aef890fc9e3d1905a5c18c96dcbc0b7f1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_PRO_BRIGHT_CTRL_MASK&#160;&#160;&#160;(0xFF &lt;&lt; 16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC BRIGHT_CTRL mask. </p>

</div>
</div>
<a class="anchor" id="a8f6ebecc8a9e684942972cd5f4479996"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_PRO_BT709_EOTF_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC BT709_EOTF mask. </p>

</div>
</div>
<a class="anchor" id="aadbf74d597b66d123380cd6e28848933"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_PRO_GAMMA_2_2_EOTF_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC GAMMA_2_2_EOTF mask. </p>

</div>
</div>
<a class="anchor" id="af9c4b47bff7449a82fc8b1c1b099034f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_PRO_GAMMA_2_6_EOTF_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC GAMMA_2_6_EOTF mask. </p>

</div>
</div>
<a class="anchor" id="a28d8d143ae40f61877646b8b76c82c67"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_PRO_LDIMM_CTRL_ACT_MASK&#160;&#160;&#160;(1&lt;&lt;13)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC Pro Seamless Local Dimming Disable Control mask. </p>

</div>
</div>
<a class="anchor" id="a83319e61d134f2b82dc3160ad445b3b7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_PRO_NTV_CS_ACT_MASK&#160;&#160;&#160;(1&lt;&lt;11)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC Pro Native Color space active mask. </p>

</div>
</div>
<a class="anchor" id="a5153613accad3ead866f9eccd11c6065"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_PRO_OF&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FYNC PRO Register offset. </p>

</div>
</div>
<a class="anchor" id="a1a7fabb9ff27d7b01f04e175c32efb89"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_PRO_PQ_EOTF_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC PQ_EOTF mask. </p>

</div>
</div>
<a class="anchor" id="acd3572d489259202bce0a73190ace2f7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_PRO_SRGB_EOTF_MASK&#160;&#160;&#160;1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC SRGB_EOTF mask. </p>

</div>
</div>
<a class="anchor" id="a4fb3f6534cc5c73d820e52d2c47a20d2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_SUPPORT_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC Support mask. </p>

</div>
</div>
<a class="anchor" id="a47d74d4099c3762aec278c25dce3dfbf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_FSYNC_VERSION_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX FSYNC Version mask. </p>

</div>
</div>
<a class="anchor" id="ae8a61a7f2bdafdc54a96e2f2f923282e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="ae4df89df74ea61966284a00390fc2754"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_AVI_CS_MASK&#160;&#160;&#160;0x03</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status AVI colorspace mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ad4f280e6064c750dcc09cdd3bdcaa408">XV_HdmiRx1_GetAviColorSpace()</a>.</p>

</div>
</div>
<a class="anchor" id="ade847b0f35ba1afad9843e799adb7bbe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_AVI_CS_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status AVI colorspace Shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ad4f280e6064c750dcc09cdd3bdcaa408">XV_HdmiRx1_GetAviColorSpace()</a>.</p>

</div>
</div>
<a class="anchor" id="a22196adeeb4add191c26302017bfb8da"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_AVI_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status AVI infoframe mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a77f3a5723008c8604137960daa6174bd">XV_HdmiRx1_GetVideoProperties()</a>.</p>

</div>
</div>
<a class="anchor" id="a7ab9bb403ffe88b36b5ad9f8dc1b28aa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_AVI_VIC_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status AVI VIC mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ab77058d12d39a6cae1920402ad231de8">XV_HdmiRx1_GetAviVic()</a>.</p>

</div>
</div>
<a class="anchor" id="abffc2c8a5b1e99d2698108754af68ee2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_AVI_VIC_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status AVI VIC Shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ab77058d12d39a6cae1920402ad231de8">XV_HdmiRx1_GetAviVic()</a>.</p>

</div>
</div>
<a class="anchor" id="a142f0f9898ec7f1fdfe87efbf3eeaf3f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_DYN_HDR_EVT_MASK&#160;&#160;&#160;(1 &lt;&lt; 20)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Dynamic HDR packet received event mask. </p>

</div>
</div>
<a class="anchor" id="ae5429bc12ee91196b66bdad3d91bec53"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_ERR_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status New Packet mask. </p>

</div>
</div>
<a class="anchor" id="a711baf7875b3d07f131faebbce2bc7af"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_FIFO_EP_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FIFO Empty mask. </p>

</div>
</div>
<a class="anchor" id="aae25cf4177044c69ea8981519b5ff454"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_FIFO_FL_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FIFO Full mask. </p>

</div>
</div>
<a class="anchor" id="aef8262d6088e54669226459118cdae1f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_FSYNC_CD_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;22)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FSYNC CD mask. </p>

</div>
</div>
<a class="anchor" id="a27b0a9a2dc2e2d4e567e6f2a9d5413d3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_FSYNC_RDY_SHIFT&#160;&#160;&#160;24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FSYNC RDY shift. </p>

</div>
</div>
<a class="anchor" id="adb74b7eab29b6ddea685e95b17e85cbd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_GCP_AVMUTE_MASK&#160;&#160;&#160;(1&lt;&lt;31)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP avmute mask. </p>

</div>
</div>
<a class="anchor" id="a6e4260d14636c843678d98e6c6cb6648"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_GCP_CD_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;25)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP ColorDepth mask. </p>

</div>
</div>
<a class="anchor" id="a42156911fe2a4d3c5ac885ab25f63008"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_GCP_CD_MASK&#160;&#160;&#160;0x03</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP colordepth mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a4c6e4ca31c0b284eaa58924dd42d1d13">XV_HdmiRx1_GetGcpColorDepth()</a>.</p>

</div>
</div>
<a class="anchor" id="aa32fc692224b983ed8c19d6667bcb3d8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_GCP_CD_SHIFT&#160;&#160;&#160;26</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP colordepth Shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a4c6e4ca31c0b284eaa58924dd42d1d13">XV_HdmiRx1_GetGcpColorDepth()</a>.</p>

</div>
</div>
<a class="anchor" id="ad8888f01766a3c2663dbae99e1bbdf25"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_GCP_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status General control packet mask. </p>

</div>
</div>
<a class="anchor" id="ae0dca7c1eb9891f5021107ba4f8600e3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_GCP_PP_MASK&#160;&#160;&#160;0x07</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP pixel phase mask. </p>

</div>
</div>
<a class="anchor" id="aa0c7dd62a11c1e1bb3991484530abac5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_GCP_PP_SHIFT&#160;&#160;&#160;28</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status GCP pixel phase Shift. </p>

</div>
</div>
<a class="anchor" id="a63d7aee7a102a56cf637518d13307a12"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a8f725f6fec863ae9577ea9f2633d8672"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_NEW_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status New Packet mask. </p>

</div>
</div>
<a class="anchor" id="a1ff1aa131b92f22cdadf41f72b41de10"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ad4f280e6064c750dcc09cdd3bdcaa408">XV_HdmiRx1_GetAviColorSpace()</a>, <a class="el" href="xv__hdmirx1_8h.html#ab77058d12d39a6cae1920402ad231de8">XV_HdmiRx1_GetAviVic()</a>, <a class="el" href="xv__hdmirx1_8h.html#a4c6e4ca31c0b284eaa58924dd42d1d13">XV_HdmiRx1_GetGcpColorDepth()</a>, <a class="el" href="xv__hdmirx1_8h.html#a77f3a5723008c8604137960daa6174bd">XV_HdmiRx1_GetVideoProperties()</a>, and <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a2e3307e88b0574b011aeb988375a091e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_VRR_CD_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;21)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status VRR CD mask. </p>

</div>
</div>
<a class="anchor" id="a678dd837feda71420c60dc2588a46db3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_STA_VRR_RDY_SHIFT&#160;&#160;&#160;23</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status VRR RDY shift. </p>

</div>
</div>
<a class="anchor" id="a8a951608e8917bc25eb1f8a339650967"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_VTEM_BASE_REFRESH_RATE_MASK&#160;&#160;&#160;((0x3FF) &lt;&lt; 16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX VTEM Base refresh rate mask. </p>

</div>
</div>
<a class="anchor" id="a55d917991044df301851eeeb3623e88d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_VTEM_BASE_VFRONT_MASK&#160;&#160;&#160;((0xFF) &lt;&lt; 8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX VTEM Reduced blanking mask. </p>

</div>
</div>
<a class="anchor" id="ae32c85b9d53de97722713750479ce5f4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_VTEM_FVA_FACT_M1_MASK&#160;&#160;&#160;((0xF) &lt;&lt; 2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX VTEM FVA Factor minus 1 mask. </p>

</div>
</div>
<a class="anchor" id="ac485a09c3c426c340310b6203177840b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_VTEM_M_CONST_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX VTEM M_CONST mask. </p>

</div>
</div>
<a class="anchor" id="a7093a8c20be4f88fbd0fa90af073c813"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_VTEM_NEXT_TFR_MASK&#160;&#160;&#160;((0x1F) &lt;&lt; 27)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX VTEM Next transfer rate mask. </p>

</div>
</div>
<a class="anchor" id="af2a5e3d2cee8f59c1fd5038fa30210e6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_VTEM_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_AUX_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX VTEM Register offset. </p>

</div>
</div>
<a class="anchor" id="a7378ef7ea017959041c7e4950126866b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_VTEM_QMS_EN_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX VTEM QMS Enable mask. </p>

</div>
</div>
<a class="anchor" id="a1a4ed1a0301fd76c707434392a8267f3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_VTEM_RB_MASK&#160;&#160;&#160;(1&lt;&lt;26)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX VTEM Reduced blanking mask. </p>

</div>
</div>
<a class="anchor" id="a3f8869ac167a6200811478930459c1d7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_AUX_VTEM_VRR_EN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX VTEM VRR Enable mask. </p>

</div>
</div>
<a class="anchor" id="abadc9136ced82249f70e07e254289521"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_LANE_LOCK_CHG0_MASK&#160;&#160;&#160;(1&lt;&lt;12)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word aligner tap select changed lane 0 mask. </p>

</div>
</div>
<a class="anchor" id="a94dc312749fdf9a840aede23f3800544"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_LANE_LOCK_CHG1_MASK&#160;&#160;&#160;(1&lt;&lt;13)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word aligner tap select changed lane 1 mask. </p>

</div>
</div>
<a class="anchor" id="a285820aa856b28b4cdaf13ac2f9b66b5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_LANE_LOCK_CHG2_MASK&#160;&#160;&#160;(1&lt;&lt;14)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word aligner tap select changed lane 2 mask. </p>

</div>
</div>
<a class="anchor" id="a366da1bd6d5beb7e7b588cc7f032c984"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_LANE_LOCK_CHG3_MASK&#160;&#160;&#160;(1&lt;&lt;15)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Word aligner tap select changed lane 3 mask. </p>

</div>
</div>
<a class="anchor" id="a9db246d6864fa36907e4328865361617"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_LANE_LOCK_CHGALL_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Word aligner tap select changed all lanes mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a01fb2daa2e91e2578d672460d8e76a31"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_LANE_LOCK_CHGALL_SHIFT&#160;&#160;&#160;12</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Word aligner tap select changed all lanes mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="aa7d3866d8c4fe0eb40668892c8907a6e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL word aligner tap select changed register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ad22edcce4ae3218c3f636eb90a64638b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHG0_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word aligner tap select changed lane 0 mask. </p>

</div>
</div>
<a class="anchor" id="ad19b9ec98349945260a33d590ed82b8b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHG1_MASK&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word aligner tap select changed lane 1 mask. </p>

</div>
</div>
<a class="anchor" id="a010c0a848e4f8bcee9abea98663922c1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHG2_MASK&#160;&#160;&#160;(1&lt;&lt;10)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word aligner tap select changed lane 2 mask. </p>

</div>
</div>
<a class="anchor" id="ab31ae65332d2db183a0a22b71fad3551"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHG3_MASK&#160;&#160;&#160;(1&lt;&lt;11)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Word aligner tap select changed lane 3 mask. </p>

</div>
</div>
<a class="anchor" id="ae71ca916fc1e751c0f5721bade5ab3b6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHGALL_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Word aligner tap select changed all lanes mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a3d000d222218f9abca8a2dabd6626936"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_SCRM_LOCK_CHGALL_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Word aligner tap select changed all lanes mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="aceb903127dc18e063143a5e9a63b1757"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_SKEW_LOCK_CHG_MASK&#160;&#160;&#160;(1&lt;&lt;16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word aligner tap select changed lane 0 mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="afabc42d9f5e367abca6bf7e82c4fcc9b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_WA_LOCK_CHG0_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word aligner tap select changed lane 0 mask. </p>

</div>
</div>
<a class="anchor" id="ae6c47612994744b602bbd9d3ec420474"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_WA_LOCK_CHG1_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word aligner tap select changed lane 1 mask. </p>

</div>
</div>
<a class="anchor" id="aa97364353f5889e64fdb0f2d79dbc87e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_WA_LOCK_CHG2_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word aligner tap select changed lane 2 mask. </p>

</div>
</div>
<a class="anchor" id="a0c90cd98ac9cd239267827bfe5342770"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_WA_LOCK_CHG3_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Word aligner tap select changed lane 3 mask. </p>

</div>
</div>
<a class="anchor" id="af2f364dc06424596ccc3ad6ab2b5e547"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_WA_LOCK_CHGALL_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Word aligner tap select changed all lanes mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ac99474f377d76e370d9dde2c72fac684"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_WA_LOCK_CHGALL_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Word aligner tap select changed all lanes mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ad9f1648d81ac01691581f970b6a4ca02"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_WA_TAP_CHG0_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word aligner tap select changed lane 0 mask. </p>

</div>
</div>
<a class="anchor" id="a6cde27a94c44a2f4ada850cda21bf996"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_WA_TAP_CHG1_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word aligner tap select changed lane 1 mask. </p>

</div>
</div>
<a class="anchor" id="a7c80e7c6a06c1c6c1e37ba34bd559736"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_WA_TAP_CHG2_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Word aligner tap select changed lane 2 mask. </p>

</div>
</div>
<a class="anchor" id="ae4da0f552fe1f76b4301444c2e25ae36"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_WA_TAP_CHG3_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Word aligner tap select changed lane 3 mask. </p>

</div>
</div>
<a class="anchor" id="a9ee121571671ab263e18f314daa4e822"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DBG_STA_WA_TAP_CHGALL_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Word aligner tap select changed all lanes mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a9cc9a4f86e3821f62a929d6d560a71d7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="ad4057a137cbf824dbce306e040b82c49"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_CTRL_EDID_EN_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control EDID enable mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a7de516253c3c6e3deb0e6141be953e35">XV_HdmiRx1_DdcLoadEdid()</a>.</p>

</div>
</div>
<a class="anchor" id="a3b8e0eb851af6c285e4d2a0c9a338604"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_CTRL_HDCP_EN_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control HDCP enable mask. </p>

</div>
</div>
<a class="anchor" id="a49de50ec209773717034cf9cd694fdbb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_CTRL_HDCP_MODE_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control HDCP mode mask. </p>

</div>
</div>
<a class="anchor" id="a2e3e20ebe8b6d8378d84499355294b18"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Interrupt enable mask. </p>

</div>
</div>
<a class="anchor" id="a7f2413f14093f11dd307db13281d253b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register offset. </p>

</div>
</div>
<a class="anchor" id="ab3da38b5ded37f584afa3cdaa471ffc0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_CTRL_RMSG_CLR_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control read message clear mask. </p>

</div>
</div>
<a class="anchor" id="ad1701bdc9e14c9c171f210caee99219a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Run mask. </p>

</div>
</div>
<a class="anchor" id="ad67f0253e5d43f97490f485ff58d7de4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_CTRL_SCDC_CLR_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control SCDC clear mask. </p>

</div>
</div>
<a class="anchor" id="af1c3bf86b1639762038aecd48e26e58e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_CTRL_SCDC_EN_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control SCDC enable mask. </p>

</div>
</div>
<a class="anchor" id="adcc224b817fe9b1fd2462875cf778dc6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_CTRL_SCDC_RD_WR_EVT_EN_MASK&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control SCDC Read Write Event mask. </p>

</div>
</div>
<a class="anchor" id="a771754708a8fe2d29a65563db1a7a118"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register Set offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a7de516253c3c6e3deb0e6141be953e35">XV_HdmiRx1_DdcLoadEdid()</a>.</p>

</div>
</div>
<a class="anchor" id="adfbdf61fa82aba22cb7bb3240f6bdbfb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_CTRL_WMSG_CLR_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control write message clear mask. </p>

</div>
</div>
<a class="anchor" id="abcfd19bf175b5a1df19606aecdb38d54"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_EDID_DATA_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(11*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read EDID data offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a7de516253c3c6e3deb0e6141be953e35">XV_HdmiRx1_DdcLoadEdid()</a>.</p>

</div>
</div>
<a class="anchor" id="a184b9f548fd6200f08068baf652f324e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_EDID_RP_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read EDID read pointer offset. </p>

</div>
</div>
<a class="anchor" id="af89a39cd5eb513936da0abd0829cc94f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_EDID_SP_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read EDID segment pointer offset. </p>

</div>
</div>
<a class="anchor" id="abb393b7a8cc8cb837e91eb6b2f186ab0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_EDID_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC EDID Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8c.html#a071a1f439fe0d8c875eb7514984297a6">XV_HdmiRx1_DdcGetEdidWords()</a>.</p>

</div>
</div>
<a class="anchor" id="a41c54aba350be9952f7b1b154234c1d6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_EDID_WP_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read EDID write pointer offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a7de516253c3c6e3deb0e6141be953e35">XV_HdmiRx1_DdcLoadEdid()</a>.</p>

</div>
</div>
<a class="anchor" id="a8bbedc62df34078ef06647b7130e16f4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_HDCP_ADDRESS_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(12*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read HDCP address offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a1b06bffa2fe0f7ec948c2df2c9e7bd18">XV_HdmiRx1_DdcHdcpSetAddress()</a>.</p>

</div>
</div>
<a class="anchor" id="ada994691776136b75789d9e343b4ce08"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_HDCP_DATA_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(13*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Read HDCP data offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a00e93fe81aff1008cf3302164029d8a2">XV_HdmiRx1_DdcHdcpReadData()</a>, and <a class="el" href="xv__hdmirx1_8h.html#acfd29595f76ba68f48eb651e8c97e1b8">XV_HdmiRx1_DdcHdcpWriteData()</a>.</p>

</div>
</div>
<a class="anchor" id="aa2e6b62c7b7e30d408bd3743409310f9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_HDCP_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC HDCP Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a408d0c1659d09261cff536cf6226720c">XV_HdmiRx1_DdcGetHdcpReadMessageBufferWords()</a>, <a class="el" href="xv__hdmirx1_8h.html#a73ddb323bea902304e9078c943ffab9d">XV_HdmiRx1_DdcGetHdcpWriteMessageBufferWords()</a>, <a class="el" href="xv__hdmirx1_8h.html#a533b81d0c208429a0d535d72d183d988">XV_HdmiRx1_DdcIsHdcpReadMessageBufferEmpty()</a>, and <a class="el" href="xv__hdmirx1_8h.html#a68b8778ca3dd3b9be8cfe9315837bed7">XV_HdmiRx1_DdcIsHdcpWriteMessageBufferEmpty()</a>.</p>

</div>
</div>
<a class="anchor" id="a3f91dc6f41d5fa86e69fb60a99dffa12"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="a0f3ee618abcb6825e8e7e9860155ffc3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_BUSY_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Busy mask. </p>

</div>
</div>
<a class="anchor" id="a1696b82de3b20c5513c3ff4ee5015ba9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_EDID_WORDS_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status EDID words mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8c.html#a071a1f439fe0d8c875eb7514984297a6">XV_HdmiRx1_DdcGetEdidWords()</a>.</p>

</div>
</div>
<a class="anchor" id="a885b5e8b024ee09446052c46f7e09bf8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_EDID_WORDS_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status EDID words shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8c.html#a071a1f439fe0d8c875eb7514984297a6">XV_HdmiRx1_DdcGetEdidWords()</a>.</p>

</div>
</div>
<a class="anchor" id="a3932971d83a493d116f0a8f63737f724"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Event mask. </p>

</div>
</div>
<a class="anchor" id="ae2cef0c17f58092e296e1479464d1115"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_HDCP_1_PROT_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;11)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 1.4 protocol event flag. </p>

</div>
</div>
<a class="anchor" id="abaf7f845011f382f1d52cc9e5596c33b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_HDCP_1_PROT_MASK&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 1.4 protocol flag. </p>

</div>
</div>
<a class="anchor" id="af0d3e6ec08e4edb7c641c6ddc513072d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_HDCP_2_PROT_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;12)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 protocol event flag. </p>

</div>
</div>
<a class="anchor" id="a7df39564a89353925469e1e75868ffda"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_HDCP_2_PROT_MASK&#160;&#160;&#160;(1&lt;&lt;10)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 protocol flag. </p>

</div>
</div>
<a class="anchor" id="aa079a5050948a2f8d950e5e5dad4e83a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_HDCP_AKSV_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP AKSV event mask. </p>

</div>
</div>
<a class="anchor" id="aaf0a33f51c1375bfede67343049535a1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_HDCP_RMSG_END_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP read message buffer end event mask. </p>

</div>
</div>
<a class="anchor" id="ac65d331a8b1681442417b8a227c3e985"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_HDCP_RMSG_EP_MASK&#160;&#160;&#160;(1&lt;&lt;27)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 read message buffer empty mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a533b81d0c208429a0d535d72d183d988">XV_HdmiRx1_DdcIsHdcpReadMessageBufferEmpty()</a>.</p>

</div>
</div>
<a class="anchor" id="adfb1be15f45bd1b408c5ac07ab37ed18"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_HDCP_RMSG_NC_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP read message buffer not completed event mask. </p>

</div>
</div>
<a class="anchor" id="aee72508c9844747a42defa2b3f2ce8dc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_HDCP_RMSG_WORDS_MASK&#160;&#160;&#160;0x7FF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 read message buffer words mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a408d0c1659d09261cff536cf6226720c">XV_HdmiRx1_DdcGetHdcpReadMessageBufferWords()</a>.</p>

</div>
</div>
<a class="anchor" id="a10fc375c829dc41f2417ba5f3ebc2fe5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_HDCP_RMSG_WORDS_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 read message buffer words shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a408d0c1659d09261cff536cf6226720c">XV_HdmiRx1_DdcGetHdcpReadMessageBufferWords()</a>.</p>

</div>
</div>
<a class="anchor" id="aa097132dd0838bf692d390fc1e28cbc9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_HDCP_WMSG_EP_MASK&#160;&#160;&#160;(1&lt;&lt;11)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 write message buffer empty mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a68b8778ca3dd3b9be8cfe9315837bed7">XV_HdmiRx1_DdcIsHdcpWriteMessageBufferEmpty()</a>.</p>

</div>
</div>
<a class="anchor" id="ace0f3b7a95288004c3211af9fcbf078f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_HDCP_WMSG_NEW_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP write message buffer new event mask. </p>

</div>
</div>
<a class="anchor" id="a5adb107c4de97c736e7e7ab634212474"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_HDCP_WMSG_WORDS_MASK&#160;&#160;&#160;0x7FF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 write message buffer words mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a73ddb323bea902304e9078c943ffab9d">XV_HdmiRx1_DdcGetHdcpWriteMessageBufferWords()</a>.</p>

</div>
</div>
<a class="anchor" id="ab61a6b938d6e9f9579506c97512c7729"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_HDCP_WMSG_WORDS_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status HDCP 2.2 write message buffer words shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a73ddb323bea902304e9078c943ffab9d">XV_HdmiRx1_DdcGetHdcpWriteMessageBufferWords()</a>.</p>

</div>
</div>
<a class="anchor" id="a1e194d82be050c88db0b276f30058fc1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a4b377386dc2f94f5fb4e17fb151245ab"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_DDC_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="aaa13fb19bafee84a5297a09ac97f6a4c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_SCDC_DSC_STS_UPDT_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;14)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status 0x10 SCDC reg bit 0 Status_Update set by sink event flag. </p>

</div>
</div>
<a class="anchor" id="a7922e751c958e0db943cfe707b7ca89b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_SCDC_RD_WR_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;13)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status SCDC Read Write event flag. </p>

</div>
</div>
<a class="anchor" id="aefcdacbbc2f6a3187ba765e7a4510c3a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_SCL_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status state of the SCL input mask. </p>

</div>
</div>
<a class="anchor" id="a1df200f45cce4a44711143bb25b2514a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DDC_STA_SDA_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status state of the SDA input mask. </p>

</div>
</div>
<a class="anchor" id="a7c7f0137214f7980b048526507b4d41a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HACT_VACT&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(15*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original HActive and VActive values. </p>

</div>
</div>
<a class="anchor" id="ac26c395846b60a6eff3f40e84312bd2e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HACT_VACT_HACT_MASK&#160;&#160;&#160;(0xFFFF)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original HACT mask. </p>

</div>
</div>
<a class="anchor" id="a085af547fd0813ab2aab56ee19c6bbf5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HACT_VACT_HACT_SHIFT&#160;&#160;&#160;(16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original HACT shift. </p>

</div>
</div>
<a class="anchor" id="a25459919a144cf71e428109defb64432"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HACT_VACT_VACT_MASK&#160;&#160;&#160;(0xFFFF)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original VACT mask. </p>

</div>
</div>
<a class="anchor" id="aa9639bfe3edbda964191fce99e0c6821"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HACT_VACT_VACT_SHIFT&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original VACT shift. </p>

</div>
</div>
<a class="anchor" id="a3ab5339b2298e63b0a1ea9adf9552a8b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HBACK_HCACT&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(14*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original HBack and HCActive values. </p>

</div>
</div>
<a class="anchor" id="a33ad59621cd66368588b48003676a562"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HBACK_HCACT_HBACK_MASK&#160;&#160;&#160;(0xFFFF)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original HBACK mask. </p>

</div>
</div>
<a class="anchor" id="aa8636582f103f89563e2d8e2b0f312f7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HBACK_HCACT_HBACK_SHIFT&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original HBACK shift. </p>

</div>
</div>
<a class="anchor" id="a33673f267b7167e5bf1b9e89f73e9c58"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HBACK_HCACT_HCACT_MASK&#160;&#160;&#160;(0xFFFF)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original HCACT mask. </p>

</div>
</div>
<a class="anchor" id="a86a4d6c4205afaf33c74a624bba37357"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HBACK_HCACT_HCACT_SHIFT&#160;&#160;&#160;(16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original HCACT shift. </p>

</div>
</div>
<a class="anchor" id="ab52074178b6019af2335dc97d5a39548"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HSYNC_HFRONT&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(13*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original HFront and Hsync values. </p>

</div>
</div>
<a class="anchor" id="a43188468463b05a798f04ea6d1e64d70"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HSYNC_HFRONT_ORIG_HFRONT_MASK&#160;&#160;&#160;(0xFFFF)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original HFRONT mask. </p>

</div>
</div>
<a class="anchor" id="ac98227d95f8c6e4aac730bc6619971c5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HSYNC_HFRONT_ORIG_HFRONT_SHIFT&#160;&#160;&#160;(0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original HFRONT shift. </p>

</div>
</div>
<a class="anchor" id="a5afaf9e25105faf9e47ade7293e3af96"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HSYNC_HFRONT_ORIG_HSYNC_MASK&#160;&#160;&#160;(0xFFFF)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original HSYNC mask. </p>

</div>
</div>
<a class="anchor" id="a504f2e3dc05b5f97b3b8e154719b3736"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_DSC_CVTEM_HSYNC_HFRONT_ORIG_HSYNC_SHIFT&#160;&#160;&#160;(16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DSC original HSYNC shift. </p>

</div>
</div>
<a class="anchor" id="aad30ea73982fde5380a2833d81232f77"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_CLK_RATIO_UPD_EVT_EN_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Clock Ratio Update Event Enable mask. </p>

</div>
</div>
<a class="anchor" id="a445d11205376c2220586ddd6c01fb423"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Register Clear offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#ae387ae2d8723aa7ae9367694b70ac03f">XV_HdmiRx1_FrlLtpDetectionEnable()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a04b941fdfc281d7d81665d47ac32f1d2">XV_HdmiRx1_FrlReset()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#a0544f5226d2072e3a594677139f54d70">XV_HdmiRx1_ResetFrlLtpDetection()</a>.</p>

</div>
</div>
<a class="anchor" id="a71db0925746b66864611a70e65445328"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_DPACK_AUTO_RST_DIS_MASK&#160;&#160;&#160;(1&lt;&lt;17)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control DPACK Auto Reset Disable mask. </p>

</div>
</div>
<a class="anchor" id="a754c0697e23ed8df25ce37bbafb354fd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_DPACK_ERR_CNT_CLR_MASK&#160;&#160;&#160;(1&lt;&lt;16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control DPACK Error Counter Clear mask. </p>

</div>
</div>
<a class="anchor" id="a6df54e050460b99271edf151b9ad0f0d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_DPACK_RST_MASK&#160;&#160;&#160;(1&lt;&lt;15)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control DPACK Reset mask. </p>

</div>
</div>
<a class="anchor" id="aa929db9fe8649faf5c094fb703fd82f9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_FLT_CLR_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control FLT Clear mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#a82e80b12dafcd1984f11cbddbbd68551">XV_HdmiRx1_FrlLtpDetectionDisable()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#ae387ae2d8723aa7ae9367694b70ac03f">XV_HdmiRx1_FrlLtpDetectionEnable()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#a0544f5226d2072e3a594677139f54d70">XV_HdmiRx1_ResetFrlLtpDetection()</a>.</p>

</div>
</div>
<a class="anchor" id="afa179bd6d9cac676f9b7df1ee8ffd205"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_FLT_THRES_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control FLT Threshold mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#a095b12f733544b877279ea062c592a7d">XV_HdmiRx1_SetFrlLtpThreshold()</a>.</p>

</div>
</div>
<a class="anchor" id="a6bc624e0b0602449534d016b66261420"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_FLT_THRES_SHIFT&#160;&#160;&#160;6</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Config LTP Threshold shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#a095b12f733544b877279ea062c592a7d">XV_HdmiRx1_SetFrlLtpThreshold()</a>.</p>

</div>
</div>
<a class="anchor" id="a529c5fbb5a5dbc3e6b133550576b915d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_FRL_RATE_WR_EVT_EN_MASK&#160;&#160;&#160;(1&lt;&lt;14)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control FRL Rate Write Event Enable. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#a4806363b327ac1b624d0b470ab46c142">XV_HdmiRx1_SetFrlRateWrEvent_En()</a>.</p>

</div>
</div>
<a class="anchor" id="a7649d0a19aea029fbe8aa66aa2e7bb3f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a75abb8243e3ab51c5be8507ea4e3dec8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#a095b12f733544b877279ea062c592a7d">XV_HdmiRx1_SetFrlLtpThreshold()</a>.</p>

</div>
</div>
<a class="anchor" id="ac0543cd5347f0876ed999cf7fbe6bb0c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_RSCC_RSFC_DISP_CLR_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL RSCC Disparity Clear mask. </p>

</div>
</div>
<a class="anchor" id="a21d52c1e98512bf55931aba594323451"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_RSTN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Resetn mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#a04b941fdfc281d7d81665d47ac32f1d2">XV_HdmiRx1_FrlReset()</a>.</p>

</div>
</div>
<a class="anchor" id="a32a9590fef5f8526e7c68b2ce8e88f89"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Register Set offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#a82e80b12dafcd1984f11cbddbbd68551">XV_HdmiRx1_FrlLtpDetectionDisable()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a04b941fdfc281d7d81665d47ac32f1d2">XV_HdmiRx1_FrlReset()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a0544f5226d2072e3a594677139f54d70">XV_HdmiRx1_ResetFrlLtpDetection()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#a4806363b327ac1b624d0b470ab46c142">XV_HdmiRx1_SetFrlRateWrEvent_En()</a>.</p>

</div>
</div>
<a class="anchor" id="a98140ad3ebfd81ea887155d70d27944f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_SKEW_EVT_EN_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Skew Event Enable mask. </p>

</div>
</div>
<a class="anchor" id="ad4103d12ed12bd574602c02a0a5b300e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_VID_LOCK_CNT_CLR_MASK&#160;&#160;&#160;(1&lt;&lt;18)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Video Lock Counter Clear Mask. </p>

</div>
</div>
<a class="anchor" id="a2ddbe9d9d80c511a34e8f581f467bf69"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_CTRL_VID_LOCK_RST_DIS_MASK&#160;&#160;&#160;(1&lt;&lt;19)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Control Video Lock Reset Disable Mask. </p>

</div>
</div>
<a class="anchor" id="a566bd6a5e931c701ab04941f556b7817"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_ERR_CNT1_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(12*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Error Count Data Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a00e5be7b31aa15206b65f39be3c3725b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="aece82a4f2fafedbae117e46849c8f40a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_LNK_CLK_MASK&#160;&#160;&#160;0xFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Link Clock mask. </p>

</div>
</div>
<a class="anchor" id="a1a5393b88617a33dff7527a0c7a3f84c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_RATIO_ACT_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Total Active Data Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#abcaa2a7e3e0a31a5d19b99179e70c636">XV_HdmiRx1_GetFrlActivePixRatio()</a>.</p>

</div>
</div>
<a class="anchor" id="a9607aefecf7958adf00b11faaca7ceb0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_RATIO_TOT_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Total Data Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#afd29a2caefd6060c3546e3debe17f03b">XV_HdmiRx1_GetFrlTotalPixRatio()</a>.</p>

</div>
</div>
<a class="anchor" id="a95df122fd8f593ac94504abaff87fecb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_RSFC_CNT_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(11*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Reed-Solomon FEC Counter Data Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ac5b57521457e46c5e347db1bd1d8ac28"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_SCDC_ADDR_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL SCDC Address Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae9e628e19196bcade3dd720dc86db3a6">XV_HdmiRx1_DdcRegDump()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a38c0efa82d512c42b07775e36f919bb2">XV_HdmiRx1_FrlDdcReadField()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField()</a>.</p>

</div>
</div>
<a class="anchor" id="a642b2cfd71e9e2e80ed18b0ee2ce0674"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_SCDC_ADDR_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL SCDC Address Interrupt mask. </p>

</div>
</div>
<a class="anchor" id="afc293c2e58cd8a42b857d83e4cb388b5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_SCDC_DAT_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL SCDC Data mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField()</a>.</p>

</div>
</div>
<a class="anchor" id="a070a1c8c80d4f949700398f70e4c1184"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_SCDC_DAT_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL SCDC Data mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae9e628e19196bcade3dd720dc86db3a6">XV_HdmiRx1_DdcRegDump()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a38c0efa82d512c42b07775e36f919bb2">XV_HdmiRx1_FrlDdcReadField()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField()</a>.</p>

</div>
</div>
<a class="anchor" id="aa5500d41f17295752a46f34a3f6ca2f3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_SCDC_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Video Clock Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae9e628e19196bcade3dd720dc86db3a6">XV_HdmiRx1_DdcRegDump()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a38c0efa82d512c42b07775e36f919bb2">XV_HdmiRx1_FrlDdcReadField()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField()</a>.</p>

</div>
</div>
<a class="anchor" id="a96095a3a06333a80279343e58bd9a512"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_SCDC_RD_MASK&#160;&#160;&#160;(1&lt;&lt;17)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL SCDC Read mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae9e628e19196bcade3dd720dc86db3a6">XV_HdmiRx1_DdcRegDump()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#a38c0efa82d512c42b07775e36f919bb2">XV_HdmiRx1_FrlDdcReadField()</a>.</p>

</div>
</div>
<a class="anchor" id="aa89cb22259109c7e37ef35afa705782a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_SCDC_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;18)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL SCDC Ready mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae9e628e19196bcade3dd720dc86db3a6">XV_HdmiRx1_DdcRegDump()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a38c0efa82d512c42b07775e36f919bb2">XV_HdmiRx1_FrlDdcReadField()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField()</a>.</p>

</div>
</div>
<a class="anchor" id="affb659995dc3b980da1ecf2bea25f794"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_SCDC_WR_MASK&#160;&#160;&#160;(1&lt;&lt;16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL SCDC Write mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField()</a>.</p>

</div>
</div>
<a class="anchor" id="ab95cf4e9c8b7891357d146db4f17c12c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_CLK_RATIO_UPD_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;10)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Clock Ratio Update event mask. </p>

</div>
</div>
<a class="anchor" id="a026e659775cddab20ce2b7127d886187"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Event mask. </p>

</div>
</div>
<a class="anchor" id="a7ddf3b09dbf2981e2dd320fdb3fd3115"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_FLT_PM_ALLL_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status FLT Pattern Match All Lanes mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#af9ac94749a5d49d68879dda13618a3fd">XV_HdmiRx1_GetPatternsMatchStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="a290ac811254db762d363a1f1a69e23d3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_FLT_PM_ALLL_SHIFT&#160;&#160;&#160;3</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status FLT Pattern Match All Lanes shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__frl_8c.html#af9ac94749a5d49d68879dda13618a3fd">XV_HdmiRx1_GetPatternsMatchStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="a2721fcb8496d097ab7cf21f2f39290b4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_FLT_PM_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status FLT Pattern Match event mask. </p>

</div>
</div>
<a class="anchor" id="aa09e7df816b5b21cfd051bbaf0b43fe2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_FLT_PM_L0_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status FLT Pattern Match Lane 0 mask. </p>

</div>
</div>
<a class="anchor" id="adf6d5682c4c2464afc7f56546fb48180"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_FLT_PM_L1_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status FLT Pattern Match Lane 0 mask. </p>

</div>
</div>
<a class="anchor" id="a5f9b94d9a17d07164465effd3babde35"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_FLT_PM_L2_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status FLT Pattern Match Lane 0 mask. </p>

</div>
</div>
<a class="anchor" id="aaa7457d835c11acfbdcd51a04fd69612"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_FLT_PM_L3_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status FLT Pattern Match Lane 0 mask. </p>

</div>
</div>
<a class="anchor" id="a9d7548c9ae36cafd37124871aa47f809"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_FLT_UPD_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status FLT Update event mask. </p>

</div>
</div>
<a class="anchor" id="a819ca83e4c0169868874dc344b97e0f9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_FRL_LANES_MASK&#160;&#160;&#160;(1&lt;&lt;28)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Lanes mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a2c5d7ff6904298bf55ccaa3ad1e52209"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_FRL_MODE_MASK&#160;&#160;&#160;(1&lt;&lt;27)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Mode mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a9ce5dbbe22e0e4254cec1e5c1e791b9e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_FRL_RATE_MASK&#160;&#160;&#160;0x7</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Rate mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a9ae67cbce6039396d76e9fae77871960"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_FRL_RATE_SHIFT&#160;&#160;&#160;29</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Rate shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a19aa4846875e36f3df281003be17365b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a14fa43a8eb929f9834823a037557c755"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_LANE_LOCK_ALLL_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Lane Lock All Lanes mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="af3ce4c26d43187cdd23935f92d00772b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_LANE_LOCK_ALLL_SHIFT&#160;&#160;&#160;12</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Lane Lock All Lanes shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ab77c50ec8738b12eb34bfcc973d84b18"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_LANE_LOCK_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Lane Lock event mask. </p>

</div>
</div>
<a class="anchor" id="aefb851bc82ac01da4415eec7f0652c84"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_LANE_LOCK_L0_MASK&#160;&#160;&#160;(1&lt;&lt;12)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Lane Lock L0 mask. </p>

</div>
</div>
<a class="anchor" id="af7d24396f309b46e0d89a3c5d3e6bfa5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_LANE_LOCK_L1_MASK&#160;&#160;&#160;(1&lt;&lt;13)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Lane Lock L1 mask. </p>

</div>
</div>
<a class="anchor" id="ac8efacae8a57dca401f42c4f5f093efc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_LANE_LOCK_L2_MASK&#160;&#160;&#160;(1&lt;&lt;14)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Lane Lock L2 mask. </p>

</div>
</div>
<a class="anchor" id="a313a043679a0f8d94e34fa616a70b113"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_LANE_LOCK_L3_MASK&#160;&#160;&#160;(1&lt;&lt;15)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Lane Lock L3 mask. </p>

</div>
</div>
<a class="anchor" id="a96860e2915010d82971cc380b30d30fd"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#af9ac94749a5d49d68879dda13618a3fd">XV_HdmiRx1_GetPatternsMatchStatus()</a>, and <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ac2fe661649f7abaca976e6655434f059"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_RATE_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status FRL Rate change event mask. </p>

</div>
</div>
<a class="anchor" id="a47ebab7f2a605e29b68f2121c1bde7d7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_SCRM_LOCK_ALLL_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Scrambler All Lanes mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a4fb39fe8225243a7a63b683cde0e772c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_SCRM_LOCK_ALLL_SHIFT&#160;&#160;&#160;20</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Scrambler All Lanes shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a254e0b71e23d9491cd4a4c887439794c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_SCRM_LOCK_L0_MASK&#160;&#160;&#160;(1&lt;&lt;20)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Scrambler Lock L0 mask. </p>

</div>
</div>
<a class="anchor" id="ab4edf834fbe041b7d89216e566316313"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_SCRM_LOCK_L1_MASK&#160;&#160;&#160;(1&lt;&lt;21)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Scrambler Lock L1 mask. </p>

</div>
</div>
<a class="anchor" id="a5f29ae4406b5f11ca0b5a1005e026b90"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_SCRM_LOCK_L2_MASK&#160;&#160;&#160;(1&lt;&lt;22)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Scrambler Lock L2 mask. </p>

</div>
</div>
<a class="anchor" id="a89957a40e34b71ee90216175c42e6c24"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_SCRM_LOCK_L3_MASK&#160;&#160;&#160;(1&lt;&lt;23)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Scrambler Lock L3 mask. </p>

</div>
</div>
<a class="anchor" id="adff37a259608df74837cd1854e1a7cd6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_SKEW_LOCK_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;11)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Skew Lock event mask. </p>

</div>
</div>
<a class="anchor" id="aa1fb32957e468cc337ac7ce5828a0b50"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_SKEW_LOCK_MASK&#160;&#160;&#160;(1&lt;&lt;24)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Skew Lock mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="afdfa16dd3c11af7a70bf3743f3c5dbd3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_STR_MASK&#160;&#160;&#160;(1&lt;&lt;25)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Video STR mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="abe2e332e4def7d78b9692fcfe5dceb3a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_VID_LOCK_MASK&#160;&#160;&#160;(1&lt;&lt;26)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Video Lock mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="aa4a2f8e85cba03c8b0eb1a230b2f89c4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_WA_LOCK_ALLL_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Aligner Lock All Lanes mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a55c84609819cd4f182160813cff62ffe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_WA_LOCK_ALLL_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Aligner Lock All Lanes shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a05fb5edf2d95d4aaebecae4d77f1a7ff"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_WA_LOCK_L0_MASK&#160;&#160;&#160;(1&lt;&lt;16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Aligner Lock L0 mask. </p>

</div>
</div>
<a class="anchor" id="a863a347d86204ae241caf3b75dc830bc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_WA_LOCK_L1_MASK&#160;&#160;&#160;(1&lt;&lt;17)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Aligner Lock L1 mask. </p>

</div>
</div>
<a class="anchor" id="a9617a7728c0e6c52f9570d425785633c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_WA_LOCK_L2_MASK&#160;&#160;&#160;(1&lt;&lt;18)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Aligner Lock L2 mask. </p>

</div>
</div>
<a class="anchor" id="aae460de84f682e7c476c4475f38ca9e9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_STA_WA_LOCK_L3_MASK&#160;&#160;&#160;(1&lt;&lt;19)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Status Aligner Lock L3 mask. </p>

</div>
</div>
<a class="anchor" id="a32129335b27ab577af25798959eafb6a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_VCLK_VCKE_RATIO_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Video Clock to VCKE Ratio Register offset. </p>

</div>
</div>
<a class="anchor" id="ad3117961fb5f5cff41d33e2c0f35eecc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_VID_CLK_MASK&#160;&#160;&#160;0xFFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL Video Clock mask. </p>

</div>
</div>
<a class="anchor" id="a49b8c41fcbbd455844d641a215d6eae8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_FRL_VID_LOCK_CNT_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_FRL_BASE)+(13*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Video Lock Count Data Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>, and <a class="el" href="xv__hdmirx1_8h.html#a8c36e5246bc11755fd3041843a4c0183">XV_HdmiRx1_RegisterDebug()</a>.</p>

</div>
</div>
<a class="anchor" id="ab0b72058c3659fc9bbb2c202270bd1a2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_HW_H_</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Prevent circular inclusions by using protection macros. </p>

</div>
</div>
<a class="anchor" id="a411e9845d9812a9370460df4d352d1e1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiRx1_In32&#160;&#160;&#160;Xil_In32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Input Operations. </p>

</div>
</div>
<a class="anchor" id="a0ea4dac580c41d65c59984742c93fcaf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_LNKSTA_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Register Clear offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a303808819a246fb16be7b208ec3b4ebf">XV_HdmiRx1_ClearLinkStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="adf40e22e8f2c99293f379a117807d84d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_LNKSTA_CTRL_ERR_CLR_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Error Clear mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a303808819a246fb16be7b208ec3b4ebf">XV_HdmiRx1_ClearLinkStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="ae1e79cbc38e074f009b92ccb96660faf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_LNKSTA_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a7a69f20270689c5abfbee2b0db6cc7a0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_LNKSTA_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Register offset. </p>

</div>
</div>
<a class="anchor" id="a4b0867e14c060bc025e48a9ad4fd4384"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_LNKSTA_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a23eec7113adc6c29ad2a46331582ae29"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_LNKSTA_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Control Register Set offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a303808819a246fb16be7b208ec3b4ebf">XV_HdmiRx1_ClearLinkStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="a1414ccd756a611744cbfe8bb88e16f48"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_LNKSTA_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="a87138c8927cdc27db845edb3556a82c8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_LNKSTA_LNK_ERR0_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Link Error Counter Channel 0 Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a0cc1226093e566991849c308ebf9343a">XV_HdmiRx1_GetLinkStatus()</a>.</p>

</div>
</div>
<a class="anchor" id="a5d7731b44b7ab0d771dcf9864b45c470"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_LNKSTA_LNK_ERR1_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Link Error Counter Channel 1 Register offset. </p>

</div>
</div>
<a class="anchor" id="a98ae4b2e8422beaf711f1c9549a21851"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_LNKSTA_LNK_ERR2_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Link Error Counter Channel 2 Register offset. </p>

</div>
</div>
<a class="anchor" id="ac8d20de61b9c7d747c78d766aeaec51c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_LNKSTA_STA_ERR_MAX_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Status Maximum Errors mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a1ba7daadc574d5f04ca24a9afc4da31b">XV_HdmiRx1_IsLinkStatusErrMax()</a>.</p>

</div>
</div>
<a class="anchor" id="affc58e86fdd9965c66c1787293747fe7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_LNKSTA_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ae1aaa652d8211c7cc612dd506aeb480d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_LNKSTA_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>LNKSTA Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>, <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>, and <a class="el" href="xv__hdmirx1_8h.html#a1ba7daadc574d5f04ca24a9afc4da31b">XV_HdmiRx1_IsLinkStatusErrMax()</a>.</p>

</div>
</div>
<a class="anchor" id="a090582e52a472f924918d70505f62b11"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_MASK_16&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>16 bit mask value </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx1__selftest_8c.html#abaa46cfd50c028ac5b941638dceb7bb7">XV_HdmiRx1_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="a80876cd6b8704c0ad0aa94767e6e9b67"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiRx1_Out32&#160;&#160;&#160;Xil_Out32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Output Operations. </p>

</div>
</div>
<a class="anchor" id="ab783565a557552b6340347c74fa21ad9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="ab295c07286c024627e6b5dd1abc99451"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="aad8520194df2924611a96f965a5f57c6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control register offset. </p>

</div>
</div>
<a class="anchor" id="a9ba54758033579b93394c923fa15dceb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Run mask. </p>

</div>
</div>
<a class="anchor" id="aad7f2e6a3f83a5b545340458f0d696ca"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register Set offset. </p>

</div>
</div>
<a class="anchor" id="aa303f116af14392fe13aebd0cc78a125"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_ID&#160;&#160;&#160;0x2200</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO ID. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx1__selftest_8c.html#abaa46cfd50c028ac5b941638dceb7bb7">XV_HdmiRx1_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="af194c444b1a273aed3950eca10ca1135"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Identification register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx1__selftest_8c.html#abaa46cfd50c028ac5b941638dceb7bb7">XV_HdmiRx1_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="af4dcda505ba0f225b5b8c9cb9a3c1389"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_ALIGNER_LOCK_MASK&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In alinger lock mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a04e11b499092095ce68d48fc3f40e04c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_BRDG_OVERFLOW_MASK&#160;&#160;&#160;(1&lt;&lt;10)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In bridge overflow mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a106ccba962224187a330b068ddd772c1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_DET_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In cable detect mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a5223536dada6b7c9610aea11ae7a190b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_DSC_EN_STRM_CHG_EVT_MASK&#160;&#160;&#160;(1 &lt;&lt; 11)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This bit is present in PIO_IN_EVT reg only. </p>
<p>It is set by IP when the DSC packets are present in stream. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="add83a38ee29484b49b58d3557b78622e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_DSC_EN_STRM_MASK&#160;&#160;&#160;(1 &lt;&lt; 11)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In DSC packets present in stream. </p>

</div>
</div>
<a class="anchor" id="ad9a3ed590d3044b9978cdcd1a20abe06"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_DSC_PPS_PKT_ERR_MASK&#160;&#160;&#160;(1 &lt;&lt; 12)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This bit is preset in PIO_IN_EVT reg only. </p>
<p>This bit is set when DSC packet errors are present. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a84f86b84d6ad904b4c48821aacd45533"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_EVT_FE_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(12*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Falling Edge Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a1b566a2b83360e0a9712dec14f7d19a3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_EVT_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Register offset. </p>

</div>
</div>
<a class="anchor" id="a0560f28ec4c56a00c8922c127fabcbee"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_EVT_RE_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(11*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Rising Edge Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a4ac3277902c44edfcce1cc6c8afcf2e3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_LNK_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In link ready mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a9e9029db2aff750b7c208c8eca7faff9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_MODE_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Mode mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a49992379740fbcb1480c2ea6aa8709c2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>, and <a class="el" href="xv__hdmirx1_8h.html#a6c66ee7dbad42980fb2297404ee4fa7a">XV_HdmiRx1_GetTmdsClockRatio()</a>.</p>

</div>
</div>
<a class="anchor" id="ac0cdb812388d2c6c671cc5e884eed62f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_SCDC_SCRAMBLER_ENABLE_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In SCDC scrambler enable mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a51d2852cd78f9a896e224454b97f092b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_SCDC_TMDS_CLOCK_RATIO_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In SCDC TMDS clock ratio mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx1_8h.html#a6c66ee7dbad42980fb2297404ee4fa7a">XV_HdmiRx1_GetTmdsClockRatio()</a>.</p>

</div>
</div>
<a class="anchor" id="afd4fb120b78254f2d9c8d7291f6854f2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_SCRAMBLER_LOCK0_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Scrambler lock 0 mask. </p>

</div>
</div>
<a class="anchor" id="a7ff42e4cf86eae3a34b4d1f708be8902"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_SCRAMBLER_LOCK1_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Scrambler lock 1 mask. </p>

</div>
</div>
<a class="anchor" id="a4d492282755dc2c57fa68144da30f2d9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_SCRAMBLER_LOCK2_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Scrambler lock 2 mask. </p>

</div>
</div>
<a class="anchor" id="a7d01e744c692ff9a143309dd407196a9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_SCRAMBLER_LOCKALLL_MASK&#160;&#160;&#160;0xF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Scrambler lock all lanes mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="afbf01122ade2aaaf05f758fb22095341"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_SCRAMBLER_LOCKALLL_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Scrambler lock all lanes shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a7e39e0c95a43c2962ee66c1a45f3fbed"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_IN_VID_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In video ready mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ab7fa4573aef8cdef877bb782670b5dd2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_AXIS_EN_MASK&#160;&#160;&#160;0x80000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Axis Enable mask. </p>

</div>
</div>
<a class="anchor" id="ab38c46f5b81c2bfd313314921cf5c275"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_BRIDGE_PIXEL_MASK&#160;&#160;&#160;(1&lt;&lt;30)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Bridge_Pixel drop mask. </p>

</div>
</div>
<a class="anchor" id="af5b360bef2825b063ec1d6a4f5cfe55a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_BRIDGE_YUV420_MASK&#160;&#160;&#160;(1&lt;&lt;29)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Bridge_YUV420 mask. </p>

</div>
</div>
<a class="anchor" id="a9f3ee5ffefea5fea81b6278347ac0911"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register Clear offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#af441b03cc79286c209dbffed19fc6052">XV_HdmiRx1_EXT_SYSRST()</a>, <a class="el" href="xv__hdmirx1_8h.html#aba149130be3e337c3789bd0fcf3c8481">XV_HdmiRx1_EXT_VRST()</a>, <a class="el" href="xv__hdmirx1_8h.html#a50135eae0f23d244548816d4c08893f4">XV_HdmiRx1_INT_LRST()</a>, <a class="el" href="xv__hdmirx1_8h.html#a54c8f8e466187861aeeb7f1de53839c4">XV_HdmiRx1_INT_VRST()</a>, and <a class="el" href="xv__hdmirx1_8h.html#ac7552beea455de7ac51452cb284241f3">XV_HdmiRx1_SetHpd()</a>.</p>

</div>
</div>
<a class="anchor" id="a686038ae877f6ad613ca1eb8d6e20596"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_COLOR_SPACE_MASK&#160;&#160;&#160;0xC00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Space mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ac9cfa9c40125304ad6b85cc1c88d3b52">XV_HdmiRx1_SetColorFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="ab91524f2e3868ea812c5e9a6e6a877ec"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_COLOR_SPACE_SHIFT&#160;&#160;&#160;10</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Space shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ac9cfa9c40125304ad6b85cc1c88d3b52">XV_HdmiRx1_SetColorFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="a452a30d01e4984cc21070aeed8440edb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_DEEP_COLOR_MASK&#160;&#160;&#160;0x30</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Deep Color mask. </p>

</div>
</div>
<a class="anchor" id="a6a6ba1381257dd1757b5296d1482a14b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_DEEP_COLOR_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Deep Color shift. </p>

</div>
</div>
<a class="anchor" id="a7e60d62918e48ee2e27bfc0064d3863d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_DYN_HDR_DM_EN_MASK&#160;&#160;&#160;(1 &lt;&lt; 23)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Dynamic HDR Data Mover enable mask. </p>

</div>
</div>
<a class="anchor" id="af4e73625cd9540a0f4885dd41afd95eb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_EXT_SYSRST_MASK&#160;&#160;&#160;(1&lt;&lt;22)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out EXT_SYSRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#af441b03cc79286c209dbffed19fc6052">XV_HdmiRx1_EXT_SYSRST()</a>.</p>

</div>
</div>
<a class="anchor" id="a67959c83fa1faaaccb685a9070cec447"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_EXT_VRST_MASK&#160;&#160;&#160;(1&lt;&lt;21)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out EXT_VRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aba149130be3e337c3789bd0fcf3c8481">XV_HdmiRx1_EXT_VRST()</a>.</p>

</div>
</div>
<a class="anchor" id="ad0879431e9c01049409338523d61c179"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_HPD_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Hot-Plug Detect mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ac7552beea455de7ac51452cb284241f3">XV_HdmiRx1_SetHpd()</a>.</p>

</div>
</div>
<a class="anchor" id="a40d80538fcb5bc6ae4dd18590766b12c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_INT_LRST_MASK&#160;&#160;&#160;(1&lt;&lt;20)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out INT_LRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a50135eae0f23d244548816d4c08893f4">XV_HdmiRx1_INT_LRST()</a>.</p>

</div>
</div>
<a class="anchor" id="a12d07ceb2b0cf661463eace18d19b370"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_INT_VRST_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out INT_VRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a54c8f8e466187861aeeb7f1de53839c4">XV_HdmiRx1_INT_VRST()</a>.</p>

</div>
</div>
<a class="anchor" id="a9664bc1a8eba4759abae05a526070145"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_LNK_EN_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out video enable mask. </p>

</div>
</div>
<a class="anchor" id="acdedab9c5aa955316fd71fcf8597ba83"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_MSK_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Mask Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ac9cfa9c40125304ad6b85cc1c88d3b52">XV_HdmiRx1_SetColorFormat()</a>, and <a class="el" href="xv__hdmirx1_8h.html#a8a1adaddc73691394f2f181411fffdc7">XV_HdmiRx1_SetPixelRate()</a>.</p>

</div>
</div>
<a class="anchor" id="a2762aba9d45253971668c25e35400e3f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ac9cfa9c40125304ad6b85cc1c88d3b52">XV_HdmiRx1_SetColorFormat()</a>, and <a class="el" href="xv__hdmirx1_8h.html#a8a1adaddc73691394f2f181411fffdc7">XV_HdmiRx1_SetPixelRate()</a>.</p>

</div>
</div>
<a class="anchor" id="a478987cdc818e2083db0f500ef6b66ab"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_PIXEL_RATE_MASK&#160;&#160;&#160;0xC0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Pixel Rate mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a8a1adaddc73691394f2f181411fffdc7">XV_HdmiRx1_SetPixelRate()</a>.</p>

</div>
</div>
<a class="anchor" id="a3177edd91ed0cd44227a908abcd854ca"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_PIXEL_RATE_SHIFT&#160;&#160;&#160;6</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Pixel Rate Shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a8a1adaddc73691394f2f181411fffdc7">XV_HdmiRx1_SetPixelRate()</a>.</p>

</div>
</div>
<a class="anchor" id="a40633ba82555b5031c1d8fcce419bf3e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_PP_MASK&#160;&#160;&#160;0x70000</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Pixel Phase mask. </p>

</div>
</div>
<a class="anchor" id="a562f10222f58d4c0debc2227ef9b8247"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_PP_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Pixel Phase shift. </p>

</div>
</div>
<a class="anchor" id="aca9ae5b99ad8d51e238bd4837a8cc2da"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_RESET_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Reset mask. </p>

</div>
</div>
<a class="anchor" id="acb55268d76c753b98f3b5d991f0cb5a0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_SAMPLE_RATE_MASK&#160;&#160;&#160;0x300</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Sample Rate mask. </p>

</div>
</div>
<a class="anchor" id="a7aa254b975a393b0e6b1b05026fb2e13"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_SAMPLE_RATE_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Sample Rate shift. </p>

</div>
</div>
<a class="anchor" id="a373757bf8fb4bca95302a14fc014a878"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_SCRM_MASK&#160;&#160;&#160;(1&lt;&lt;12)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Scrambler mask. </p>

</div>
</div>
<a class="anchor" id="ada35683dde8266cadc45f975707d577b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register Set offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#af441b03cc79286c209dbffed19fc6052">XV_HdmiRx1_EXT_SYSRST()</a>, <a class="el" href="xv__hdmirx1_8h.html#aba149130be3e337c3789bd0fcf3c8481">XV_HdmiRx1_EXT_VRST()</a>, <a class="el" href="xv__hdmirx1_8h.html#a50135eae0f23d244548816d4c08893f4">XV_HdmiRx1_INT_LRST()</a>, <a class="el" href="xv__hdmirx1_8h.html#a54c8f8e466187861aeeb7f1de53839c4">XV_HdmiRx1_INT_VRST()</a>, and <a class="el" href="xv__hdmirx1_8h.html#ac7552beea455de7ac51452cb284241f3">XV_HdmiRx1_SetHpd()</a>.</p>

</div>
</div>
<a class="anchor" id="a519c487569199868a3cb9e63ca31c741"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_OUT_VID_EN_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out video enable mask. </p>

</div>
</div>
<a class="anchor" id="aef8c2bdce4282861650f4b2c24b4bf58"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_STA_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Status Event mask. </p>

</div>
</div>
<a class="anchor" id="a0d4a80745016667fabf3927fb58bc835"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a010800518b582144dfb9dcc66525faf6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PIO_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_PIO_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="af3377eb2df940c5697d67f58e08cd20f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_PKT_ECC_ERR_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Packet ECC Error Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a851cb0524c797d3ce8380b1c27b9a17f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiRx1_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__hdmirx1__hw_8h.html#a411e9845d9812a9370460df4d352d1e1">XV_HdmiRx1_In32</a>((BaseAddress) + (RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro reads a value from a HDMI RX register. </p>
<p>A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the HDMI RX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xv__hdmirx1__hw_8h.html#a851cb0524c797d3ce8380b1c27b9a17f" title="This macro reads a value from a HDMI RX register. ">XV_HdmiRx1_ReadReg(UINTPTR BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, <a class="el" href="xv__hdmirx1_8c.html#a071a1f439fe0d8c875eb7514984297a6">XV_HdmiRx1_DdcGetEdidWords()</a>, <a class="el" href="xv__hdmirx1_8h.html#a408d0c1659d09261cff536cf6226720c">XV_HdmiRx1_DdcGetHdcpReadMessageBufferWords()</a>, <a class="el" href="xv__hdmirx1_8h.html#a73ddb323bea902304e9078c943ffab9d">XV_HdmiRx1_DdcGetHdcpWriteMessageBufferWords()</a>, <a class="el" href="xv__hdmirx1_8h.html#a00e93fe81aff1008cf3302164029d8a2">XV_HdmiRx1_DdcHdcpReadData()</a>, <a class="el" href="xv__hdmirx1_8h.html#a533b81d0c208429a0d535d72d183d988">XV_HdmiRx1_DdcIsHdcpReadMessageBufferEmpty()</a>, <a class="el" href="xv__hdmirx1_8h.html#a68b8778ca3dd3b9be8cfe9315837bed7">XV_HdmiRx1_DdcIsHdcpWriteMessageBufferEmpty()</a>, <a class="el" href="xv__hdmirx1_8h.html#ae9e628e19196bcade3dd720dc86db3a6">XV_HdmiRx1_DdcRegDump()</a>, <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>, <a class="el" href="xv__hdmirx1_8h.html#aa8d5e2d39022661864bdf89e0fca6b3d">XV_HdmiRx1_DynHDR_GetInfo()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a38c0efa82d512c42b07775e36f919bb2">XV_HdmiRx1_FrlDdcReadField()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField()</a>, <a class="el" href="xv__hdmirx1_8h.html#ad6862d6b700903b0fde41c14f49c56ef">XV_HdmiRx1_GetAcrCts()</a>, <a class="el" href="xv__hdmirx1_8h.html#ad372b661989dfb070a6931b88aadad86">XV_HdmiRx1_GetAcrN()</a>, <a class="el" href="xv__hdmirx1_8h.html#ad4f280e6064c750dcc09cdd3bdcaa408">XV_HdmiRx1_GetAviColorSpace()</a>, <a class="el" href="xv__hdmirx1_8h.html#ab77058d12d39a6cae1920402ad231de8">XV_HdmiRx1_GetAviVic()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#abcaa2a7e3e0a31a5d19b99179e70c636">XV_HdmiRx1_GetFrlActivePixRatio()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#afd29a2caefd6060c3546e3debe17f03b">XV_HdmiRx1_GetFrlTotalPixRatio()</a>, <a class="el" href="xv__hdmirx1_8h.html#a4c6e4ca31c0b284eaa58924dd42d1d13">XV_HdmiRx1_GetGcpColorDepth()</a>, <a class="el" href="xv__hdmirx1_8h.html#a0cc1226093e566991849c308ebf9343a">XV_HdmiRx1_GetLinkStatus()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#af9ac94749a5d49d68879dda13618a3fd">XV_HdmiRx1_GetPatternsMatchStatus()</a>, <a class="el" href="xv__hdmirx1_8h.html#a6c66ee7dbad42980fb2297404ee4fa7a">XV_HdmiRx1_GetTmdsClockRatio()</a>, <a class="el" href="xv__hdmirx1_8h.html#a77f3a5723008c8604137960daa6174bd">XV_HdmiRx1_GetVideoProperties()</a>, <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>, <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>, <a class="el" href="xv__hdmirx1_8h.html#a1ba7daadc574d5f04ca24a9afc4da31b">XV_HdmiRx1_IsLinkStatusErrMax()</a>, <a class="el" href="xv__hdmirx1_8h.html#a8c36e5246bc11755fd3041843a4c0183">XV_HdmiRx1_RegisterDebug()</a>, <a class="el" href="xv__hdmirx1__selftest_8c.html#abaa46cfd50c028ac5b941638dceb7bb7">XV_HdmiRx1_SelfTest()</a>, and <a class="el" href="xv__hdmirx1__frl_8c.html#a095b12f733544b877279ea062c592a7d">XV_HdmiRx1_SetFrlLtpThreshold()</a>.</p>

</div>
</div>
<a class="anchor" id="a44f9bde6a5097e3b1c287447e8292f87"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_SHIFT_16&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>16 shift value </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, and <a class="el" href="xv__hdmirx1__selftest_8c.html#abaa46cfd50c028ac5b941638dceb7bb7">XV_HdmiRx1_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="a601ed84adad6a742a16572b1394049f7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_SR_SSB_ERR1_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL SR/SSB period error during training period mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a65be302ae67526fd5247ed8bb7d992eb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_SR_SSB_ERR1_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL SR/SSB period error during training period shift. </p>

</div>
</div>
<a class="anchor" id="ace563a6b75eaca93062466c5fb31d3c8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_SR_SSB_ERR2_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL SR/SSB period error during NON-training period mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a505ad0065028146badda00bb46ef8100"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_SR_SSB_ERR2_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>FRL SR/SSB period error during NON-training period shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="adfbfa70ecfc15e9951eed4a41333b8e1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_SR_SSB_ERR_CNT0_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>SR/SSB period error 0 counter register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ae366ca39c9b39631eedf90c9df008502"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_SR_SSB_ERR_CNT1_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>SR/SSB period error 1 counter register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a38593421477cf0920a8c26ca2cc02844"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_SR_SSB_ERR_CNT2_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>SR/SSB period error 2 counter register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a280f061931e044ccdc8aa667114f17e5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_SR_SSB_ERR_CNT3_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>SR/SSB period error 3 counter register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a293fd830851198f7e914a854331b5896"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR1_CNT_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Counter Register offset. </p>

</div>
</div>
<a class="anchor" id="ac3f7fead56ecd78e386866c94c088e4b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR1_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a4971c7cbae30577c586eb34bddec2aac"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR1_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a8540999b4f1e41b762f357cc838e5584"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR1_STA_CNT_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Status counter Event mask. </p>

</div>
</div>
<a class="anchor" id="aeae47d24687bc43e32160a9308182746"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR2_CNT_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Counter Register offset. </p>

</div>
</div>
<a class="anchor" id="ab49a117151e93626b4c4e6cfaa88fbca"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR2_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a2efd70def06239d90d9cfa77a554b478"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR2_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a5a941faa36f4859e301a361c9001f99b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR2_STA_CNT_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Status counter Event mask. </p>

</div>
</div>
<a class="anchor" id="ae3314caa4470dc986d1d7a50f1de62c9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR3_CNT_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Counter Register offset. </p>

</div>
</div>
<a class="anchor" id="aa49f4509e6046355bfdd463e060bf81d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR3_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="afeea10b36e6aae8f6924ff77a9f16989"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR3_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a262bcc996ce3a05ce2b5e69405164625"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR3_STA_CNT_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Status counter Event mask. </p>

</div>
</div>
<a class="anchor" id="a2b45e7f59deb365e580565110ec1be4e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR4_CNT_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Counter Register offset. </p>

</div>
</div>
<a class="anchor" id="ad4ccd558833c924e452e41b04f4aad67"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR4_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a404594f6834c97a323eccb1f6acf10e4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR4_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a2c6dbfd3edb699863544439e29145230"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR4_STA_CNT_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Status counter Event mask. </p>

</div>
</div>
<a class="anchor" id="a1cdf2bc260e7b4039352ef7cea5638b9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Register Clear offset. </p>

</div>
</div>
<a class="anchor" id="ac12ef34573fbbdd3716faff94534dbdc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control register offset. </p>

</div>
</div>
<a class="anchor" id="a3d6d8df87e3d66f70c7517431b791a10"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Control Register Set offset. </p>

</div>
</div>
<a class="anchor" id="a96e1c2a18841fcfcc91736e225ce603c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Identification register offset. </p>

</div>
</div>
<a class="anchor" id="af91d2f9f96e679cac7647029f58ec4f7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a4afca904429b1f2e882bea212effe1cf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TMR_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_TMR_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TMR Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a161cbe93ae2eadf4572c49ddac875dd9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_ANLZ_LN_ACT_ACT_SZ_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte analyzer act size mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a2e6a5f0f7a7eb7fd3ca5c02672995617"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_ANLZ_LN_ACT_ACT_SZ_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte analyzer act size shift. </p>

</div>
</div>
<a class="anchor" id="a117109a90e42e3017e55fbfc7ebd9966"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_ANLZ_LN_ACT_LN_SZ_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte analyzer line act mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="aae138c58ab74045375d385644647ebf5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_ANLZ_LN_ACT_LN_SZ_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte analyzer line act shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="af450e13abf1a60b31de267c985fffbaa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_ANLZ_LN_ACT_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(11*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte Analyzer Line Size Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a5bbac44be7ff425765198c35f15ee990"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_ANLZ_TIM_CHGD_CNT_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte analyzer timing changed count mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ad90bee32417f21768fc9b165ef2b39e1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_ANLZ_TIM_CHGD_CNT_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte analyzer timing changed count shift. </p>

</div>
</div>
<a class="anchor" id="a25030374b218ae27a165342023eb26f6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_ANLZ_TIM_HS_POL_MASK&#160;&#160;&#160;(1&lt;&lt;17)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte analyzer timing hsync polarity mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ad74412e1cce4c05dc20962e823caaa2e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_ANLZ_TIM_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte Analyzer Timing Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="aefd7163342d38fe7440ac8cb178bb734"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_ANLZ_TIM_VS_POL_MASK&#160;&#160;&#160;(1&lt;&lt;16)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte analyzer timing vsync polarity mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a1cef14123da432543b502426ea4ba921"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_HBP_HS_HBP_SZ_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte hbp size mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ac1ff018afd4c825fae5d24a0d99397c8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_HBP_HS_HBP_SZ_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte hbp size shift. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a290b6094a24ee78187d80ce9e3bac2bf"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_HBP_HS_HS_SZ_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte hsync size mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a08ce749b52f9176223488d5436c10d2a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_HBP_HS_HS_SZ_SHIFT&#160;&#160;&#160;0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte hsync size shift. </p>

</div>
</div>
<a class="anchor" id="a8ecc8705595c3f5ef2efdefea908ef19"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_TRIB_HBP_HS_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_LNKSTA_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Tri-byte HBP_HS Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a7c9d08be5e87e6fd62df99abfd8d3a07"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VCKE_SYS_CNT_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VCKE System Counts Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a98c2ec7a077e707ff67302d576ba468f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VER_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VER Identification Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="a8b63858c4f1f73528819cac7258bc730"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VER_VERSION_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VER_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VER Version Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#a13af54cb5eac5be1f950b9f9ee4773a7">XV_HdmiRx1_DebugInfo()</a>.</p>

</div>
</div>
<a class="anchor" id="ae6e5fdc512cb7dc4f87aa5ddf8d87044"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_ACT_LIN_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Active Lines Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="aaf231b8bf27d043648c5d4c18570e109"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_ACT_PIX_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Active Pixels Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="ae971e94da9cfb5a7a9b682ae3526bb44"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Clear Register offset. </p>

</div>
</div>
<a class="anchor" id="a4e137d48421d51cab3ab2292ac749f0c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_CTRL_FIELD_POL_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control field polarity mask. </p>

</div>
</div>
<a class="anchor" id="a778b05c24de8ad264eb1fe2cc33e88af"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a38f34bcb7e8f5d9de99c03aacd27353b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Register offset. </p>

</div>
</div>
<a class="anchor" id="ad3255aafdf1db8869d62b1ab51d58ad0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a373df61175a1b81c8c49973a7c429c8a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control Set Register offset. </p>

</div>
</div>
<a class="anchor" id="a52153a206da2f6de52a47e4a96f70df9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_CTRL_SYNC_LOSS_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control field polarity mask. </p>

</div>
</div>
<a class="anchor" id="aceaecabf406db886ed55dfe8f36abddc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_CTRL_TIMEBASE_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control timebase shift. </p>

</div>
</div>
<a class="anchor" id="ac0f972a680a7e327fd805030bba7d7c6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_CTRL_TIMERBASE_MASK&#160;&#160;&#160;0xffffff</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Control timebase mask. </p>

</div>
</div>
<a class="anchor" id="a0d60962ac4dd676e0835f784cb4fa8b3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_CTRL_VFP_ENABLE_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD VFP change interrupt enable mask. </p>

</div>
</div>
<a class="anchor" id="a29d81fca1318aa8e6dcb266ebf3eaf49"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_HBP_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(14*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Horizontal Back Porch Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="aefb8dcc326ae1f421f1755d7eae42f2c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_HFP_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(13*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Horizontal Front Porch Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="ad49d4b9701fc528d4b35be9e0e0784b6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_HSW_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Horizontal Sync Width Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="aef7c0f8c9f534cc7dbc8720d5a8911bb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_ID_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Identification Register offset. </p>

</div>
</div>
<a class="anchor" id="a1d7f91b7dd9418376b0f3b3ad33dffa9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_STA_FMT_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Status Format mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="ac65a4d1a61da0cc29958b992c6096bc7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_STA_HS_POL_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Status Hsync Polarity mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="a979add2356c64b6b17d2e173b148a223"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a7520909f353bdbc6da5cf59e436c0346"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_STA_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Status Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>, and <a class="el" href="xv__hdmirx1__intr_8c.html#aa63dbee16a4d7face7e6d6aa49bef361">XV_HdmiRx1_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a36d63214bbba54dc596c75254384db59"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_STA_SYNC_LOSS_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Status Sync Loss mask. </p>

</div>
</div>
<a class="anchor" id="a580a0780c855eae7a5be6d14eaed70e0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_STA_TIMEBASE_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Status timebase event mask. </p>

</div>
</div>
<a class="anchor" id="a95f2fd6152ac185b6fe4b47420610202"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_STA_VFP_CH_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Status Vfp value chage mask. </p>

</div>
</div>
<a class="anchor" id="a8451cdcae193a13f05a07d2b1d7c46f5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_STA_VS_POL_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Status Vsync Polarity mask. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="a1130ed99163f49891fe76e84a2fd1ee0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_TOT_LIN_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Total Lines Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="a31173bdc12d5d7c393e0ec4169a0e9bc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_TOT_PIX_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Total Pixels Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="a655cb29d88325aab2476894e18a858fe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_VBP_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(12*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Vertical Back Porch Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="a8b283a7d946febcf50815dc8ad31bf8d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_VFP_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(11*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Vertical Front Porch Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="a881c6ffd3db18a7af39fe337d00eb179"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMIRX1_VTD_VSW_OFFSET&#160;&#160;&#160;((XV_HDMIRX1_VTD_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>VTD Vertical Sync Width Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#aeb4be084a07a96cd89d3f4386fbadae2">XV_HdmiRx1_GetVideoTiming()</a>.</p>

</div>
</div>
<a class="anchor" id="a949523423dffb540041a98a38e283cf8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiRx1_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__hdmirx1__hw_8h.html#a80876cd6b8704c0ad0aa94767e6e9b67">XV_HdmiRx1_Out32</a>((BaseAddress) + (RegOffset), (u32)(Data))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro writes a value to a HDMI RX register. </p>
<p>A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the HDMI RX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file) to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write into the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmirx1__hw_8h.html#a949523423dffb540041a98a38e283cf8" title="This macro writes a value to a HDMI RX register. ">XV_HdmiRx1_WriteReg(UINTPTR BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmirx1_8h.html#ae8f2b92316ba8599c678aa9168d2eb24">XV_HdmiRx1_CfgInitialize()</a>, <a class="el" href="xv__hdmirx1_8h.html#a303808819a246fb16be7b208ec3b4ebf">XV_HdmiRx1_ClearLinkStatus()</a>, <a class="el" href="xv__hdmirx1_8h.html#a1b06bffa2fe0f7ec948c2df2c9e7bd18">XV_HdmiRx1_DdcHdcpSetAddress()</a>, <a class="el" href="xv__hdmirx1_8h.html#acfd29595f76ba68f48eb651e8c97e1b8">XV_HdmiRx1_DdcHdcpWriteData()</a>, <a class="el" href="xv__hdmirx1_8h.html#a7de516253c3c6e3deb0e6141be953e35">XV_HdmiRx1_DdcLoadEdid()</a>, <a class="el" href="xv__hdmirx1_8h.html#ae9e628e19196bcade3dd720dc86db3a6">XV_HdmiRx1_DdcRegDump()</a>, <a class="el" href="xv__hdmirx1_8h.html#aadab16501ebe113f3881aa7c7d2091f1">XV_HdmiRx1_DynHDR_SetAddr()</a>, <a class="el" href="xv__hdmirx1_8h.html#af441b03cc79286c209dbffed19fc6052">XV_HdmiRx1_EXT_SYSRST()</a>, <a class="el" href="xv__hdmirx1_8h.html#aba149130be3e337c3789bd0fcf3c8481">XV_HdmiRx1_EXT_VRST()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a38c0efa82d512c42b07775e36f919bb2">XV_HdmiRx1_FrlDdcReadField()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#ab17e4f96ebbe6785b411233165de859a">XV_HdmiRx1_FrlDdcWriteField()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a82e80b12dafcd1984f11cbddbbd68551">XV_HdmiRx1_FrlLtpDetectionDisable()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#ae387ae2d8723aa7ae9367694b70ac03f">XV_HdmiRx1_FrlLtpDetectionEnable()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a04b941fdfc281d7d81665d47ac32f1d2">XV_HdmiRx1_FrlReset()</a>, <a class="el" href="xv__hdmirx1_8h.html#a50135eae0f23d244548816d4c08893f4">XV_HdmiRx1_INT_LRST()</a>, <a class="el" href="xv__hdmirx1_8h.html#a54c8f8e466187861aeeb7f1de53839c4">XV_HdmiRx1_INT_VRST()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a0544f5226d2072e3a594677139f54d70">XV_HdmiRx1_ResetFrlLtpDetection()</a>, <a class="el" href="xv__hdmirx1_8h.html#ac9cfa9c40125304ad6b85cc1c88d3b52">XV_HdmiRx1_SetColorFormat()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a095b12f733544b877279ea062c592a7d">XV_HdmiRx1_SetFrlLtpThreshold()</a>, <a class="el" href="xv__hdmirx1__frl_8c.html#a4806363b327ac1b624d0b470ab46c142">XV_HdmiRx1_SetFrlRateWrEvent_En()</a>, <a class="el" href="xv__hdmirx1_8h.html#ac7552beea455de7ac51452cb284241f3">XV_HdmiRx1_SetHpd()</a>, and <a class="el" href="xv__hdmirx1_8h.html#a8a1adaddc73691394f2f181411fffdc7">XV_HdmiRx1_SetPixelRate()</a>.</p>

</div>
</div>
</div><!-- contents -->
</div><!-- doc-content -->
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
	<p class="footer">&copy; Copyright 2015-2022 Xilinx, Inc. All Rights Reserved.</p>
	<p class="footer">&copy; Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.</p>
</div>
</body>
</html>
